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1. WO1997013191 - ADDRESS TRANSFORMATION IN A CLUSTER COMPUTER SYSTEM

Publication Number WO/1997/013191
Publication Date 10.04.1997
International Application No. PCT/US1996/015937
International Filing Date 04.10.1996
Chapter 2 Demand Filed 07.02.1997
IPC
G06F 12/02 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
CPC
G06F 12/0284
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0223User address space allocation, e.g. contiguous or non contiguous base addressing
0284Multiple user address space allocation, e.g. using different base addresses
G06F 12/0811
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
0811with multilevel cache hierarchies
G06F 12/084
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
084with a shared cache
Applicants
  • BULL HN INFORMATION SYSTEMS INC. [US]/[US]
Inventors
  • GUENTHNER, Russell, W.
  • RABINS, Leonard
Agents
  • SOLAKIAN, John, S.
Priority Data
08/540,10606.10.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ADDRESS TRANSFORMATION IN A CLUSTER COMPUTER SYSTEM
(FR) TRANSFORMATION DES ADRESSES DANS UN SYSTEME D'ORDINATEUR ORGANISE EN GRAPPES
Abstract
(EN)
To integrate a plurality of processors (11-14), each capable of directly addressing a limited internal storage range, with a large external memory, processors are organized into clusters, each having a plurality of processors and a common secondary cache (7). An address translator (18) is provided to transform internal main memory space (8) addresses to external memory space addresses. External memory space is divided into private and shared areas. An internal address indicator bit, in conjuction with the cluster number form a requesting processor primary cache, is employed to set up the transformation either to the private external space of the cluster or the shared external space. In reverse external-to-internal transformation, a pair of indicator bits are used to generate the internal address and define the shared and private space of the designated cluster. A cluster member number assigned to each processor is used by the secondary cache to track with processor sends/receives information to/from the external memory.
(FR)
Pour procéder à l'intégration d'un ensemble de processeurs (11-14) dont chacun doit être en mesure d'adresser une portion limitée d'un espace interne de stockage, à l'aide d'un espace de mémoire externe plus vaste, lesdits processeurs sont disposés en grappes comportant chacune plusieurs processeurs et une antémémoire (7) secondaire commune. Un traducteur (18) d'adresses assure des transformations entre les adresses de l'espace (8) mémoire interne et les adresses de l'espace mémoire externe. L'espace mémoire externe est divisé en espaces privés et partagés. Un bit indicateur d'adresses internes associé au numéro de grappe forme l'antémémoire primaire d'un processeur demandeur, et sert à établir la transformation soit vers l'espace externe privé de cette grappe, soit vers l'espace externe commun. Dans la transformation inverse, de l'extérieur vers intérieur, une paire de bits indicateurs sert à générer une adresse interne et à déterminer l'espace commun et l'espace privé de la grappe désignée. Le numéro de grappe attribué à chacun des processeur est utilisé par l'antémémoire secondaire pour déterminer celui des processeurs qui émet des informations vers la mémoire externe, ou en reçoit.
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