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1. WO1996042148 - PROGRAMMABLE DATA PORT FOR ATM MEMORY

Publication Number WO/1996/042148
Publication Date 27.12.1996
International Application No. PCT/US1995/016220
International Filing Date 08.12.1995
Chapter 2 Demand Filed 02.01.1997
IPC
G06F 1/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
H04J 3/06 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
H04L 7/00 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
H04L 12/56 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
H04Q 11/04 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
QSELECTING
11Selecting arrangements for multiplex systems
04for time-division multiplexing
CPC
G06F 1/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
H04J 3/0688
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
0635Clock or time synchronisation in a network
0685Clock or time synchronisation in a node; Intranode synchronisation
0688Change of the master or reference, e.g. take-over or failure of the master
H04L 12/5601
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
5601Transfer mode dependent, e.g. ATM
H04L 2012/5627
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
5601Transfer mode dependent, e.g. ATM
5625Operations, administration and maintenance [OAM]
5627Fault tolerance and recovery
H04L 2012/5674
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
5601Transfer mode dependent, e.g. ATM
5672Multiplexing, e.g. coding, scrambling
5674Synchronisation, timing recovery or alignment
H04L 49/108
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
49Packet switching elements
10Switching fabric construction
104ATM switching fabrics
105ATM switching elements
108using shared central buffer
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • THOMANN, Mark, R.
  • VO, Huy, Thanh
  • HUSH, Glen, E.
Agents
  • VIKSNINS, Ann, S.
Priority Data
08/478,32507.06.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PROGRAMMABLE DATA PORT FOR ATM MEMORY
(FR) ACCES DE DONNEES PROGRAMMABLE POUR MEMOIRE ATM
Abstract
(EN)
A programmable multiconfiguration data port clocking system for use in asynchronous transfer mode communication (ATM) networks. The clocking system is programmed using a number of preselected configuration codes to automatically switch the clocking of the data port configuration of an ATM network chip. The clocking system incorporates an automatic disable circuit for eliminating random outputs from unused pins in the clocking hardware. The clocking system also employs a noise suppression circuit for reducing spurious noise into the ATM network.
(FR)
Système de synchronisation d'accès de données programmable pour configurations multiples, utilisable dans des réseaux de communication ATM (mode de transfert asynchrone). Le système de synchronisation est programmé au moyen d'un certain nombre de codes de configuration présélectionnés permettant de commuter automatiquement la synchronisation de la configuration d'accès de données d'une puce de réseau ATM. Le système de synchronisation comporte un circuit d'invalidation automatique permettant d'éliminer les sorties aléatoires dues aux broches inutilisées du matériel de synchronisation. Le système de synchronisation emploie également un circuit d'élimination de bruit pour réduire le bruit parasite arrivant dans le réseau ATM.
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