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1. WO1996042136 - VOLTAGE CONTROLLED OSCILLATOR WHICH IS INSENSITIVE TO POWER SUPPLY VOLTAGE NOISE

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

WHAT IS CLAIMED IS:

1. A voltage controlled oscillator comprising:

a current source;

a first transistor coupled between said current source and an output conductor wherein said first
transistor is configured with a first gate terminal connected to an input conductor and
wherein said first transistor is capable of charging said output conductor;

a second transistor coupled between said output conductor and a ground conductor wherein said
second transistor is configured with a second gate terminal connected to said input
conductor and wherein said second transistor is capable of discharging said output
conductor; and

a clamping transistor coupled between said output conductor and said ground conductor wherein
said clamping transistor is configured with a third gate terminal connected to said output conductor and wherein said clamping transistor is capable of limiting an output voltage
conveyed on said output conductor.

2. The voltage controlled oscillator as recited in claim 1 wherein said current source comprises a voltage control input conductor and wherein said current source is capable of producing a current proportional to a voltage level conveyed on said voltage control input conductor.

3. The voltage controlled oscillator as recited in claim 2 wherein said current source further comprises a pair of series-connected transistors coupled between a power supply conductor and said first transistor wherein said pair of series-connected transistors are configured with a fourth gate terminal and a fifth gate terminal and wherein said fourth gate terminal and said fifth gate terminal are coupled to said voltage control input conductor.

4. The voltage controlled oscillator as recited in claim 3 wherein said series-connected transistors are PMOS transistors.

5. The voltage controlled oscillator as recited in claim 1 wherein said first transistor is a PMOS transistor.

6. The voltage controlled oscillator as recited in claim 1 wherein said first transistor is configured with a substrate connection connected to said current source.

7. The voltage controlled oscillator as recited in claim 1 wherein said second transistor is an NMOS transistor.

8. The voltage controlled oscillator as recited in claim 1 wherein said clamping transistor is an NMOS transistor.

9. The voltage controlled oscillator as recited in claim 1 further comprising:

a third transistor coupled between said current source and a second output conductor wherein said third transistor is configured with a sixth gate terminal connected to a second input
conductor and wherein said third transistor is capable of charging said second output
conductor;

a fourth transistor coupled between said second output conductor and said ground conductor
wherein said fourth transistor is configured with a seventh gate terminal connected to said second input conductor and wherein said fourth transistor is capable of discharging said second output conductor; and

a second clamping transistor coupled between said second output conductor and said ground
conductor wherein said second clamping transistor is configured with an eighth gate
terminal connected to said second output conductor and wherein said second clamping
transistor is capable of limiting a second output voltage conveyed on said second output conductor.

10. The voltage controlled oscillator as recited in claim 9 further comprising:

a fifth transistor coupled between a third output conductor and said ground conductor wherein said fifth transistor is configured with a ninth gate terminal connected to said output conductor and wherein said fifth transistor is capable of discharging said third output conductor;

a sixth transistor coupled between said third output conductor and said power supply conductor
wherein said sixth transistor is configured with a tenth gate terminal connected to an
internal conductor and wherein said sixth transistor is capable of charging said third output conductor;

a seventh transistor coupled between said power supply conductor and said internal conductor
wherein said seventh transistor is configured with an eleventh gate terminal connected to said internal conductor and wherein said seventh transistor is capable of charging said
internal conductor; and an eighth transistor coupled between said internal conductor and said ground conductor wherein
said eighth transistor is configured with a twelfth gate terminal connected to said second output conductor and wherein said eighth transistor is capable of discharging said internal conductor.

11. The voltage controlled oscillator as recited in claim 10 further comprising an output buffer coupled to said third output conductor for providing greater driving capability for a load wherein said output buffer is an inverter circuit.

12. The voltage controlled oscillator as recited in claim 9 further comprising:

a second current source;

a ninth transistor coupled between said second current source and a fourth output conductor wherein said ninth transistor is configured with a thirteenth gate terminal connected to said output conductor and wherein said ninth transistor is capable of charging said fourth output
conductor:

a tenth transistor coupled between said fourth output conductor and said ground conductor wherein said tenth transistor is configured with a fourteenth gate terminal connected to said output conductor and wherein said tenth transistor is capable of discharging said fourth output
conductor; and

a third clamping transistor coupled between said fourth output conductor and said ground conductor wherein said third clamping transistor is configured with a fifteenth gate terminal
connected to said fourth output conductor and wherein said third clamping transistor is
capable of limiting a third output voltage conveyed on said fourth output conductor.

13. The voltage controlled oscillator as recited in claim 12 further comprising:

an eleventh transistor coupled between said second current source and a fifth output conductor
wherein said eleventh transistor is configured with a sixteenth gate terminal connected to said second output conductor and wherein said eleventh transistor is capable of charging
said fifth output conductor;

a twelfth transistor coupled between said fifth output conductor and said ground conductor wherein said twelfth transistor is configured with a seventeenth gate terminal connected to said
second output conductor and wherein said twelfth transistor is capable of discharging said fifth output conductor; and a fourth clamping transistor coupled between said fifth output conductor and said ground conductor wherein said fourth clamping transistor is configured with an eighteenth gate terminal
connected to said fifth output conductor and wherein said fourth clamping transistor is
capable of limiting a fourth output voltage conveyed on said fifth output conductor.

14. The voltage controlled oscillator as recited in claim 13 wherein said fourth output conductor is coupled to said second input conductor and wherein said fifth output conductor is coupled to said input conductor.

15. A level shifter comprising:

a first pulldown transistor coupled between an output conductor and a ground conductor wherein
said first transistor is configured with a first gate terminal connected to receive a first input signal of said level shifter and wherein said first transistor is capable of discharging said
output conductor;

a first pullup transistor coupled between said output conductor and a power supply conductor
wherein said second transistor is configured with a second gate terminal connected to an
internal conductor and wherein said second transistor is capable of charging said output
conductor:

a second pullup transistor coupled between said internal conductor and said power supply conductor wherein said third transistor is configured with a third gate terminal connected to said
internal conductor and wherein said third transistor is capable of charging said internal
conductor: and

a second pulldown transistor coupled between said internal conductor and said ground conductor
wherein said fourth transistor is configured with a fourth gate terminal connected to receive a second input signal of said level shifter and wherein said fourth transistor is capable of
discharging said internal conductor.

16. The level shifter as recited in claim 15 wherein said first pulldown transistor is an NMOS transistor.

17. The level shifter as recited in claim 15 wherein said first pullup transistor is a PMOS transistor.

18. The level shifter as recited in claim 15 wherein said second pullup transistor is a PMOS transistor.

19. The level shifter as recited in claim 15 wherein said second pulldown transistor is an NMOS transistor.

20. The level shifter as recited in claim 15 further comprising a buffer circuit coupled to said output conductor for providing greater charging capability for a load.

21. The level shifter as recited in claim 20 wherein said buffer circuit comprises an inverter circuit.

22. A method of creating an output of an oscillator which is insensitive to power supply noise comprising:

limiting the voltage of said oscillator output to a voltage range between a ground voltage and a
voltage less than a power supply voltage.

23. The method as recited in claim 22 further comprising providing a second oscillator output having a between said ground voltage and said power supply voltage.

24. The method as recited in claim 22 further comprising powering said oscillator with a power supply voltage.