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1. WO1996042105 - METHOD FOR FORMING SALICIDES

Publication Number WO/1996/042105
Publication Date 27.12.1996
International Application No. PCT/US1996/007751
International Filing Date 28.05.1996
Chapter 2 Demand Filed 02.01.1997
IPC
H01L 21/28 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H01L 21/285 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283Deposition of conductive or insulating materials for electrodes
285from a gas or vapour, e.g. condensation
H01L 21/336 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
CPC
H01L 21/28052
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
28008Making conductor-insulator-semiconductor electrodes
28017the insulator being formed after the semiconductor body, the semiconductor being silicon
28026characterised by the conductor
28035the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
28044the conductor comprising at least another non-silicon conductive layer
28052the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
H01L 21/28518
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
283Deposition of conductive or insulating materials for electrodes ; conducting electric current
285from a gas or vapour, e.g. condensation
28506of conductive layers
28512on semiconductor bodies comprising elements of Group IV of the Periodic System
28518the conductive layers comprising silicides
H01L 29/665
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
665using self aligned silicidation, i.e. salicide
Applicants
  • MATERIALS RESEARCH CORPORATION [US]/[US]
Inventors
  • FOSTER, Robert, F.
  • ARENA, Chantal
  • HILLMAN, Joseph, T.
  • AMEEN, Michael, S.
Agents
  • LUNN, Gregory, J.
  • D YOUNG & CO
Priority Data
08/489,04009.06.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR FORMING SALICIDES
(FR) PROCEDE DE FORMATION DE SALICIURES
Abstract
(EN)
Titanium is deposited onto a semiconductor interconnect to form a salicide structure by plasma-enhanced chemical vapor deposition. The reactant gases, including titanium tetrachloride, hydrogen and optionally argon, are combined. A plasma is created using RF energy and the plasma contacts the rotating semiconductor material (11). This causes titanium to be deposited which reacts with exposed silicon to form titanium silicide (67, 68 and 69) without any subsequent anneal. Other titanium deposited on the surface, as well as titanium-rich silicon compositions (TiSix wherein X is $m(f)2), are removed by chemical etching. If only about 40 Å of titanium is deposited, it will selectively deposit onto the silicon structure without coating the oxide spacers of the interconnect. In this embodiment the need to chemically etch the substrate is eliminated.
(FR)
On dépose du titane sur une interconnexion à semi-conducteurs, afin d'obtenir une structure de saliciure au moyen d'un dépôt chimique en phase vapeur au plasma. On combine les gaz réactifs, y compris le tétrachlorure de titane, l'hydrogène et, éventuellement, l'argon. On crée un plasma au moyen d'énergie haute fréquence et ce plasma vient en contact avec le matériau à semi-conducteurs (11) en rotation. Ceci provoque le dépôt du titane qui réagit avec le silicium exposé, de manière à constituer du siliciure de titane (67, 68, 69) sans recuit ultérieur. On dépose encore du titane sur la surface et on supprime par attaque chimique les compositions de silicium riche en titane (TiSix où X est $m(f)2). Si on ne dépose qu'environ 40 Å de titane, ce dernier se déposera sélectivement sur la structure de silicium sans recouvrir les éléments d'espacement en oxyde de l'interconnexion. Ce mode de réalisation permet de ne pas avoir à procéder à l'attaque chimique du substrat.
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