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1. WO1996042077 - SINGLE CENTRALISED MEMORY ARCHITECTURE FOR VIDEO IMAGE TRANSFER

Publication Number WO/1996/042077
Publication Date 27.12.1996
International Application No. PCT/FR1996/000863
International Filing Date 07.06.1996
IPC
G06T 1/60 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
60Memory management
G09G 5/39 2006.01
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36characterised by the display of individual graphic patterns using a bit-mapped memory
39Control of the bit-mapped memory
CPC
G06T 1/60
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
60Memory management
G09G 2340/10
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
2340Aspects of display data processing
10Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
G09G 5/36
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
G09G 5/39
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
39Control of the bit-mapped memory
Applicants
  • THOMPSON BROADCAST SYSTEMS [FR]/[FR] (AllExceptUS)
  • BOURRE, Thierry [FR]/[FR] (UsOnly)
  • LABRANCHE, Patrick [FR]/[FR] (UsOnly)
  • REBIAI, Mohamed [FR]/[FR] (UsOnly)
  • BRUHAT, Patrice [FR]/[FR] (UsOnly)
Inventors
  • BOURRE, Thierry
  • LABRANCHE, Patrick
  • REBIAI, Mohamed
  • BRUHAT, Patrice
Agents
  • THOMSON MULTIMEDIA
Priority Data
95/0675208.06.1995FR
Publication Language French (FR)
Filing Language French (FR)
Designated States
Title
(EN) SINGLE CENTRALISED MEMORY ARCHITECTURE FOR VIDEO IMAGE TRANSFER
(FR) ARCHITECTURE A MEMOIRE UNIQUE CENTRALISEE POUR LE TRANSFERT D'IMAGES VIDEO
Abstract
(EN)
An architecture for storing and transferring still or animated video images is disclosed. Said architecture includes at least one input circuit (E1, E2, ..., En) for video image data access, a memory area (M) for storing video images, at least one video image output circuit (S1, S2, ..., Sj) and a video bus (B) for transferring data between the memory area (M), the input circuit and the output circuit. Said memory area (M) is a working area and the width (L) of the video bus (B) is no smaller than that of the memory area (M). The working area is under the centralised control of a control circuit (CTRL). Said architecture may be used in dedicated computer platforms for transferring broadcast-quality images, or in video devices for computer-generated image animation. Said architecture may further include video image processing circuits (T1, T2, ..., Tn).
(FR)
L'invention concerne une architecture permettant de stocker et de transférer des images vidéo fixes ou animées, ladite architecture comprenant au moins un circuit d'entrée (E1, E2, ..., En) permettant l'accès de données destinées à composer des images vidéo, une zone mémoire (M) permettant de stocker des images vidéo, au moins un circuit de sortie (S1, S2, ...., Sj) d'images vidéo et un bus vidéo (B) destiné à assurer le transfert d'informations entre la zone mémoire (M), le circuit d'entrée et le circuit de sortie, caractérisé en ce que la zone mémoire (M) est une mémoire banalisée et en ce que le bus vidéo (B) a une largeur L supérieure ou égale à la largeur de la zone mémoire (M). La mémoire banalisée est commandée de façon centralisée par un circuit de contrôle (CTRL). L'invention s'applique aux plates-formes informatiques dédiées au transfert d'images de qualité Broadcast ou encore aux dispositifs vidéo pour animation d'images de synthèse. L'architecture selon l'invention peut aussi comprendre des circuits de traitement (T1, T2, ..., Tn) des images vidéo.
Also published as
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