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1. WO1996041380 - MEMORY ARRAY HAVING A MULTI-STATE ELEMENT AND METHOD FOR FORMING SUCH ARRAY OR CELLS THEREOF

Publication Number WO/1996/041380
Publication Date 19.12.1996
International Application No. PCT/US1996/009056
International Filing Date 05.06.1996
Chapter 2 Demand Filed 02.01.1997
IPC
G11C 11/56 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
H01L 27/24 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
CPC
H01L 27/24
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, ; e.g. resistance switching non-volatile memory structures
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • HARSHFIELD, Steven, T.
Agents
  • WILLIAMS, Danny, L.
Priority Data
08/486,63907.06.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY ARRAY HAVING A MULTI-STATE ELEMENT AND METHOD FOR FORMING SUCH ARRAY OR CELLS THEREOF
(FR) MATRICE MEMOIRE AVEC ELEMENT A MULTIPLES ETATS ET PROCEDE DE FORMATION D'UNE TELLE MATRICE OU DE CELLULES D'UNE TELLE MATRICE
Abstract
(EN)
A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.
(FR)
Cette invention se rapporte à un dispositif de mémoire constitué de plusieurs matrices mémoires. Chacune de ces matrices possède plusieurs cellules de mémoire, renfermant chacune une électrode définissant une zone de contact correspondante. Chaque matrice mémoire est formée par dépôt d'une couche de chalcogénure continue. Cette couche de chalcogénure, même lorsqu'elle est continue, possède des zones actives formées au-dessus des électrodes, et une couche conductrice couplant électriquement au moins une partie de ces zones actives. Cette matrice mémoire peut également comporter un volume diélectrique entourant au moins une partie de la pluralité des électrodes. Ces électrodes peuvent être des contacts, des fiches ou des colonnettes formés d'un matériau déposé dans des ouvertures pratiquées par attaque dans ledit volume diélectrique.
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