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1. WO1996041267 - DELAY REDUCTION IN TRANSFER OF BUFFERED DATA BETWEEN TWO MUTUALLY ASYNCHRONOUS BUSES

Publication Number WO/1996/041267
Publication Date 19.12.1996
International Application No. PCT/US1996/008573
International Filing Date 06.06.1996
Chapter 2 Demand Filed 19.12.1996
IPC
G06F 13/40 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
CPC
G06F 13/405
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4004Coupling between buses
4027using bus bridges
405where the bridge performs a synchronising function
G06F 13/4059
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4004Coupling between buses
4027using bus bridges
405where the bridge performs a synchronising function
4059where the synchronisation uses buffers, e.g. for speed matching between buses
Applicants
  • AST RESEARCH, INC. [US]/[US]
Inventors
  • MOTE, L., Randall, Jr.
Agents
  • ALTMAN, Daniel, E.
Priority Data
08/483,50507.06.1995US
08/510,54502.08.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DELAY REDUCTION IN TRANSFER OF BUFFERED DATA BETWEEN TWO MUTUALLY ASYNCHRONOUS BUSES
(FR) REDUCTION DU RETARD DANS LE TRANSFERT DE DONNEES MISES EN MEMOIRE TAMPON ENTRE DEUX BUS MUTUELLEMENT ASYNCHRONES
Abstract
(EN)
An interface between first and second data buses (110 and 120) includes a first bus state machine (406) which controls data transfers from the first data bus (110) to a data buffer (132). The interface includes a second bus state machine (404) which controls data transfers from the data buffer (132) to the second data bus (120). A respective valid data flag (170) for each storage location is set by the first bus state machine (406) when data are stored in the storage location (132) from the first data bus (110) and is cleared by the second bus state machine (404) when data are transferred from the storage location (132) to the second data bus (120). In order to reduce the time required to output sequential data from multiple data locations in the data buffer (132), each data valid flag (170) is synchronized independently.
(FR)
Cette invention concerne une interface (Fig. 3) entre un premier et un second bus de données (110 et 120) comportant un automate fini (406) associé au premier bus qui régit les transferts de données entre le premier bus de données (110) et une mémoire tampon des données (132) ainsi qu'un automate fini (404) associé au second bus qui régit les transferts de données entre la mémoire tampon des données (132) et le second bus de données (120). L'automate fini (406) associé au premier bus positionne un drapeau de donnée valide (170) associé à chaque emplacement mémoire lorsque des données sont stockées dans l'emplacement mémoire (132) correspondant, à partir du premier bus de données (110) et l'automate fini (404) associé au second bus remet cet indicateur à zéro lorsque les données sont transférées de l'emplacement mémoire (132) vers le second bus de données (120). Afin de réduire le temps nécessaire à la sortie de données séquentielles à partir de multiples emplacements de données de la mémoire tampon (132), chaque drapeau de donnée valide (170) est synchronisé indépendamment.
Also published as
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