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1. WO1996041266 - SPLIT BUFFER ARCHITECTURE

Publication Number WO/1996/041266
Publication Date 19.12.1996
International Application No. PCT/US1996/009934
International Filing Date 06.06.1996
Chapter 2 Demand Filed 30.12.1996
IPC
G06F 5/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
5Methods or arrangements for data conversion without changing the order or content of the data handled
06for changing the speed of data flow, i.e. speed regularising
G06F 12/02 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
CPC
G06F 12/023
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0223User address space allocation, e.g. contiguous or non contiguous base addressing
023Free address space management
G06F 2205/064
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2205Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
06Indexing scheme relating to groups G06F5/06 - G06F5/16
064Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation
G06F 5/06
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
5Methods or arrangements for data conversion without changing the order or content of the data handled
06for changing the speed of data flow, i.e. speed regularising ; or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor;
Applicants
  • EMULEX CORPORATION [US]/[US]
Inventors
  • RICKARD, Wayne
  • FIACCO, Peter
  • CHAU, Vi
Agents
  • LAND, John
Priority Data
08/484,59207.06.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SPLIT BUFFER ARCHITECTURE
(FR) ARCHITECTURE DE MEMOIRE TAMPON DIVISEE
Abstract
(EN)
A partitioned memory (45) is divided into a number of large buffers (60), and one or more of the large buffers is divided to create an equal number of small buffers (65). Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.
(FR)
Une mémoire cloisonnée (45) est divisée en plusieurs mémoires tampons (60) de grande taille et une ou plusieurs de ces mémoires tampons sont divisées, de manière à créer un nombre égal de petites mémoires tampons (65). Chaque mémoire tampon de grande taille restante est associée à une petite mémoire tampon et on peut accéder à ces mémoires tampons appariées au moyen d'un pointeur unique. Les curseurs sont rangés dans une unité FIFO (premier entré, premier sorti), afin de créer un regroupement de paires de mémoires tampons disponibles.
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