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1. WO1996039698 - CELL PLATE REFERENCING FOR DRAM SENSING

Publication Number WO/1996/039698
Publication Date 12.12.1996
International Application No. PCT/US1996/009070
International Filing Date 04.06.1996
Chapter 2 Demand Filed 02.01.1997
IPC
G11C 11/4074 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4094 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4094Bit-line management or control circuits
CPC
G11C 11/4074
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4094
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4094Bit-line management or control circuits
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • SEYYEDY, Mirmajid
Agents
  • VIKSNINS, Ann, S, @ .
  • WILLIAMS, Danny, L.
Priority Data
08/471,86106.06.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CELL PLATE REFERENCING FOR DRAM SENSING
(FR) CELLULES EN PLAQUES A REFERENCES POUR DETECTION DRAM
Abstract
(EN)
An integrated circuit dynamic memory device is described which stores data in memory cells as a charge on a capacitor. The memory cells have a common cell plate and can be selectively connected to a digit line. Sensing circuitry, including both p-sense and n-sense amplifiers, is connected to the digit line and the cell plate. Equalization circuitry is described to equalize the cell plate and digit line for sensing data stored on a memory cell. Isolation circuitry is described for selectively isolating the sensing circuitry from the memory cells.
(FR)
La présente invention concerne un dispositif de mémoire dynamique en circuit intégré, qui stocke sous forme de charge d'un condensateur les données dans des cellules mémoire. Les cellules mémoire, implantées sur une plaque commune, peuvent se connecter sélectivement à une ligne chiffre. La logique de lecture, ainsi que ses amplificateurs de polarisation p et n, est connectée à la ligne chiffre ainsi qu'à la plaque des cellules. L'invention concerne également une logique d'égalisation servant à l'égalisation entre la plaque des cellules et la ligne chiffre à l'occasion de la lecture de l'information stockée dans une cellule de mémoire. L'invention concerne enfin une logique d'isolement permettant d'isoler sélectivement des cellules mémoire la logique de lecture.
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