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1. WO1996039004 - TRANSFERRING DATA IN A MULTI-PORT DRAM

Publication Number WO/1996/039004
Publication Date 05.12.1996
International Application No. PCT/US1995/015802
International Filing Date 07.12.1995
Chapter 2 Demand Filed 30.12.1996
IPC
H04L 12/56 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
CPC
H04L 12/5601
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
5601Transfer mode dependent, e.g. ATM
H04L 2012/5627
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
5601Transfer mode dependent, e.g. ATM
5625Operations, administration and maintenance [OAM]
5627Fault tolerance and recovery
H04L 2012/5652
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
5601Transfer mode dependent, e.g. ATM
5638Services, e.g. multimedia, GOS, QOS
5646Cell characteristics, e.g. loss, delay, jitter, sequence integrity
5652Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
H04L 2012/5681
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
54Store-and-forward switching systems
56Packet switching systems
5601Transfer mode dependent, e.g. ATM
5678Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
5681Buffer or queue management
H04L 49/108
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
49Packet switching elements
10Switching fabric construction
104ATM switching fabrics
105ATM switching elements
108using shared central buffer
H04L 49/405
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
49Packet switching elements
40Physical details, e.g. power supply, mechanical construction or backplane
405Physical details, e.g. power supply, mechanical construction or backplane of ATM switches
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • THOMANN, Mark, R.
  • VO, Huy, Thanh
  • HUSH, Glen, E.
Agents
  • VIKSNINS, Ann, S.
Priority Data
08/456,52001.06.1995US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TRANSFERRING DATA IN A MULTI-PORT DRAM
(FR) TRANSFERT DE DONNEES DANS UNE MEMOIRE RAM DYNAMIQUE A ACCES MULTIPLES
Abstract
(EN)
An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.
(FR)
Cette invention concerne un commutateur à mode de transfert asynchrone (ATM) contenant une mémoire à accès multiples constituée d'une mémoire dynamique à accès sélectif (DRAM) et d'une pluralité de mémoires à accès séquentiel (SAM) d'entrée et de sortie. Les circuits et procédés efficaces de transfert souple décrits permettent de transférer des données du mode de transfert asynchrone entre les mémoires SAM et la mémoire DRAM. Ces circuits et procédés de transfert incluent des bascules auxiliaires qui servent à verrouiller les données du mode de transfert asynchrone en vue de leur édition avant leur stockage en mémoire DRAM. L'édition des données du mode de transfert asynchrone transférées à partir de la mémoire DRAM est également décrite. La génération de parité dynamique et la vérification aux fins de la détection des erreurs introduites en cours de commutation sont également décrites.
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