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1. WO1996038919 - A PROGRAMMABLE OPTIMIZED-DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD

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[ EN ]

CLAIMS
We claim:

1. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method comprising:
coupling each product-term cluster in a plurality of product-term clusters to a
different input line of a programmable logic allocator;
configuring said logic allocator so that each output line of said logic allocator has programmable access to a first predetermined number of product-term clusters in said
plurality of product- term clusters;
wherein said first predetermined
number of product-term clusters includes
at least twenty product terms; and
upon programmably connecting a
product-term cluster to an output line
of said logic allocator, said connected
product-term cluster is disconnected
from all remaining output lines of said
logic allocator.

2. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 1, wherein configuring said logic allocator further comprises:
configuring said logic allocator so that a set of said output lines of said logic allocator has programmable access to both said first
predetermined number of product-term clusters and a second predetermined number of produc -term clusters in said plurality of product-term
clusters.

3. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 2 wherein a sum-of -product terms in said first predetermined number and said second predetermined number of product-term clusters is in the range of from twenty product terms to one-half of the product terms in said plurality of product-term clusters.

4. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 3, wherein the sum-of -product terms in said first predetermined number and said second predetermined number of product-term clusters is one-half of the product terms in said plurality of product-term
clusters.

5. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 3, wherein one-half of the product terms in said plurality of product-term clusters is thirty- two product terms.

6. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 3, wherein the sum-of -product terms in said first predetermined number and said second predetermined number of product-term clusters is less than one-half of the product terms in plurality of product-term clusters and greater than twenty product terms.

7. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 6, wherein the sum-of -product terms in said first predetermined number and said second predetermined number of product-term clusters is twenty-four product terms.

8. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 6, wherein the sum-of -product terms in said first predetermined number and said second predetermined number of product- term clusters twenty-eight product terms.

9. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 4, wherein said set of said output lines
comprises ten output lines.

10. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 6, wherein said set of said output lines
comprises four output lines.

11. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 7, wherein set of said output lines comprises two output lines.

12. A method for distributing product terms from a programmable array in a very high-density CPLD to logic in said very high-density CPLD, said method as in Claim 8, wherein set of said output lines comprises two output lines.

13. In an integrated circuit, a programmable optimized-distribution logic allocator comprising:
a plurality of N input lines where N is an integer;
a plurality of N output lines; and
a plurality of programmable router elements with each programmable router element having an output terminal connected to an output line in
said plurality of N output lines;
wherein each programmable router element programmably couples and decouples said
output terminal from at least five input
lines in said plurality of N input lines so
that each output line has programmable access to all input signals on a minimum of five
input lines in said plurality of N input
lines; and
upon programmably coupling the input
line- to the output terminal of one
programmable router element, the coupled
input line is decoupled all remaining output terminals of said programmable router
elements.

14. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 13 wherein one programmable router element in said
plurality of programmable router elements comprises:
a programmable demultiplexer having an input terminal connected to an input line in said
plurality of N input lines; and a plurality of M output terminals where M is one-half the value Of N;
wherein said input terminal is
programmably connectable to and
disconnectable from said plurality of M
output terminals; and
upon programmably connecting said input terminal to one of said plurality of M output terminals, said input terminal is
disconnected from all other output terminals in said plurality of M output terminals.

15. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 14 wherein said one programmable router element further comprises:
a logic gate having a plurality of M input terminals; and
an output terminal
wherein each input terminal is connected to an output terminal of a different
programmable demultiplexer.

16. In an -integrated circuit, a programmable optimized-distribution logic allocator as in Claim 15 wherein said one programmable router element further comprises:
an exclusive-OR gate having an input terminal connected to said output terminal of said logic gate, and an output terminal connected to one of said plurality of N output lines.

17. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 15 wherein said logic gate output terminal is connected to one of said plurality of N output lines.

18. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 15 wherein M is eight.

19. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 15 said plurality of programmable router elements
comprises a set of said one programmable router element;
wherein said set of said one programmable router element includes said one programmable
router element; and
each router element in said set of said one programmable router element is connected to a
different input line in said plurality of N input lines and to a different output line in said
plurality of N output lines.

20. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 19 wherein said set of said one programmable router element comprises ten of said one programmable router element.

21. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 15 wherein another one programmable router element in said plurality of programmable router elements comprises:
a programmable demultiplexer having an input terminal connected to an input line in said
plurality of N input lines; and a plurality of
(M-n) output terminals where n is an integer in a range of from 1 to 3;
wherein said input terminal is
programmably connectable to and
disconnectable from said plurality of (M-n) output terminals; and
upon programmably connecting said input terminal to one of said plurality of N output terminals, said input terminal is
disconnected from all other output terminals in said plurality of (M-n) output terminals.

22. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 21 wherein said another one programmable router element further comprises:
a logic gate having a plurality of (M-n)
input terminals; and
an output terminal
wherein each input terminal is connected to an output terminal of a different
programmable demultiplexer.

23. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 22 wherein said another one programmable router element further comprises:
an exclusive-OR gate having an input terminal connected to said output terminal of said logic gate, and an output terminal connected to one of said plurality of N output lines.

24. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 22 wherein said logic gate output terminal is connected to one of said plurality of N output lines.

25. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 22 wherein M is eight.

26. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 22 said plurality of programmable router elements
comprises a set of said another one programmable router element;
wherein said set of said another one
programmable router element includes said another one programmable router element; and
each router element in said set of said
another one programmable router element is
connected to a different input line in said
plurality of N input lines and to a different
output line in said plurality of N output lines.

27. In an integrated circuit, a programmable optimized-distribution logic allocator as in Claim 26 wherein said set of said another one programmable router element comprises two of said another one programmable router element.

28. In an integrated circuit, a programmable optimized-distribution logic allocator comprising:
a plurality of N input lines where N is an integer;
a plurality of N output lines where N is an integer;
a multiplicity of programmable router
elements comprising:
a first plurality of programmable router elements;
wherein an output terminal of each
router element in said first plurality
of programmable router elements is
connected to a different output line in
said plurality of N output lines; and
each router element in said first plurality of programmable router
elements is programmably connectable to and disconnectable from at least M input lines in said plurality of N input lines so that each logic allocator output line connected to one of said router elements in said first plurality of programmable router elements has programmable access to all input signals on M input lines in said plurality of N input lines where M is an integer;
a second plurality of programmable router elements;
wherein an output terminal of each
router element in said second plurality of programmable router elements is connected to to a different output line in said plurality of N output lines; and
each router element in said second
plurality of programmable router elements is programmably connectable to and
disconnectable from at least (M-n) input
lines in said plurality of logic allocator input lines so that each logic allocator
output line connected to one of said router elements in said second plurality of
programmable router elements has programmable access to all input signals on (M-n) input lines in said plurality of N input lines
where n is an integer in a range from 1 to 3 and M is selected so that when n is three,
(M-n) is at least five.