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1. WO1996031005 - OUTPUT CHARACTERISTICS STABILIZATION OF CMOS DEVICES

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[ EN ]

Claims :

1. An apparatus for driving an unterminated data bus having a plurality of threads, comprising:
a) a current source of substantially known and stable current; b) a representative MOS transistor having a drain coupled to said current source, a source coupled to a first voltage rail, and a gate, said representative MOS transistor being of a known relative first size;
c) a plurality of output devices, each output device having a bus driver, and each bus driver having a first MOS transistor having a source coupled to said first voltage rail, a drain coupled to a respective of the plurality of threads of said data bus, and a gate coupled to said gate of said representative MOS transistor such that each first MOS transistor, when ON, mirrors a characteristic of said representative MOS transistor, each first MOS transistor being of a substantially identical known relative second size, wherein
said representative MOS transistor conducts said known and stable current from said current source, and each of said plurality of bus drivers, when ON, scalingly mirrors the
characteristic of said representative MOS transistor as a function of said relative second size and said relative first size, and
said representative MOS transistor and said plurality of output devices are located on a single chip.

2. An apparatus according to claim 1, wherein:
each said output device further includes an inverter coupled between said current source and said first voltage rail, said inverter having a bit control input, and said inverter having an output coupled to said gate of said first MOS
transistor.

3. An apparatus according to claim 1, wherein:
said inverter comprises a second MOS transistor of a first type and a third MOS transistor of a second type different than said first type, said second MOS transistor having a source coupled to said current source, a gate coupled to said bit control input for said respective output device, and a drain coupled to said gate of said first MOS transistor, and said third MOS transistor having a source coupled to said first voltage rail, a drain coupled to said drain of said second MOS transistor and to said gate of said first MOS transistor, and a gate coupled to said gate of said second MOS transistor and to said control input for said respective output device.

4. An apparatus according to claim 1, further comprising:
buffer means coupled between said current source and said plurality of output devices.

5. An apparatus according to claim 1 , wherei :
said gate of said representative MOS transistor is connected to said drain of said representative MOS transistor, and
said characteristic is a saturation current.

6. An apparatus according to claim 3, wherein:
said gate of said representative MOS transistor is connected to said drain of said representative MOS transistor, and
said characteristic is a saturation current.

7. An apparatus according to claim 6, further comprising:
buffer means coupled between said current source and said plurality of output devices.

8. An apparatus according to claim 1, wherein:
said current source comprises voltage means coupled to a second voltage rail for generating a voltage which is known and fixed relative to said second voltage rail, a first resistor coupled to said second voltage rail, an operational amplifier having first and second inputs and an output, said first input being coupled to said voltage means and receiving said voltage which is known and fixed relative to said second voltage rail, and said second input being coupled to said first resistor, and transistor means coupled to said first resistor, to said drain of said representative transistor, and to said output of said operational amplifier, wherein said operational amplifier causes a fixed current to be pulled through said first resistor.

9. An apparatus according to claim 8, wherein:
said voltage means comprises a second resistor and a Zener diode, said Zener diode coupled between said second voltage rail and said second resistor, and said second resistor coupled between said first voltage rail and said first input of said operational amplifier.

10. An apparatus according to claim 8, wherein:
said transistor means coupled to said first resistor comprises a p-type bipolar transistor having an emitter coupled to said first resistor, a base coupled to said output of said operational amplifier, and a collector coupled to said drain of said representative MOS transistor.

11. An apparatus according to claim 10, wherein:
said current source further comprises a follower buffer having a first input coupled to said collector of said p-type bipolar transistor, and a second input and an output coupled to each other, wherein said output of said follower buffer is also coupled to said plurality of output devices.

12. An apparatus according to claim 11, wherein:
said current source further comprises a first capacitor coupled between said collector of said p-type bipolar transistor and said first voltage rail, and a second capacitor coupled between said output of said follower buffer and said first voltage rail.

13. An apparatus according to claim 1, wherein:
said characteristic is an RQN characteristic of said representative transistor, said apparatus further comprising means for controlling the RON characteristic of said representative MOS transistor, wherein the RO of said bus driver is inversely proportional to said ratio.

14. An apparatus according to claim 13, wherein:
said means for controlling comprises an operational
amplifier means with first and second inputs and an output, a voltage source means with a controlled output voltage, and a MOS control transistor with a source, a drain, and a gate, wherein said drain of said representative MOS transistor and said controlled output voltage are respectively coupled to said first and second inputs of said operational amplifier means, said output of said operational amplifier means is coupled to said gate of said MOS control transistor, said source of said MOS control transistor is coupled to said gate of said
representative MOS transistor, and said drain of said MOS control transistor is coupled to said first voltage rail.

15. An apparatus according to claim 14, wherein:
said means for controlling further comprises a first resistor coupled between a second voltage rail and said gate of said representative MOS transistor.

16. An apparatus according to claim 15, wherein:
said voltage source means comprises a band-gap reference voltage source coupled to said first voltage rail and providing a first voltage, second and third resistors arranged as a voltage divider between said first voltage rail and said band-gap reference voltage source, wherein said controlled output voltage is taken from said voltage divider.

17. An apparatus according to claim 1, wherein:
said current source comprises a voltage source means coupled to said first voltage rail for generating a voltage which is known and fixed relative to said first voltage rail, a first resistor coupled to said first voltage rail, an
operational amplifier having first and second inputs and an output, said first input being coupled to said voltage source means and receiving said voltage which is known -and fixed relative to said first voltage rail, and said second input being coupled to said first resistor, a first current source
transistor coupled to said first resistor and to said output of said first voltage rail, and second and third current source transistors coupled together and arranged as a current mirror with said second current source transistor coupled to said first current source transistor, and said third current source transistor coupled to said drain of said representative MOS transistor.

18. An apparatus according to claim 17, wherein:
said first current source transistor has a gate coupled to said output of said operational amplifier, a source coupled to said first resistor, and a drain,
said second current source transistor has a drain and a gate coupled to said drain of said first current source
transistor, and a source coupled to a second voltage rail, and said third current source transistor has a source coupled to said second voltage rail, a drain coupled to said drain of said representative MOS transistor, and a gate coupled to said gate of said second current source transistor.

19. An apparatus according to claim 14, wherein:
said current source includes said voltage source means, a first resistor coupled to said first voltage rail, a second operational amplifier having first and second inputs and an output, said first input being coupled to said voltage source means, and said second input being coupled to said first resistor, a first current source transistor coupled to said first resistor and to said output of said first voltage rail, and second and third current source transistors coupled together and arranged as a current mirror with said second current source transistor coupled to said first current source transistor, and said third current source transistor coupled to said drain of said representative MOS transistor.

20. An apparatus according to claim 19, wherein:
said first current source transistor has a gate coupled to said output of said second operational amplifier, a source coupled to said first resistor, and a drain,
said second current source transistor has a drain and a gate coupled to said drain of said first current source
transistor, and a source coupled to a second voltage rail, and
said third current source transistor has a source coupled to said second voltage rail, a drain coupled to said drain of said representative MOS transistor, and a gate coupled to said gate of said second current source transistor.

21. An apparatus according to claim 20, wherein:
said voltage source means comprises a band-gap reference voltage source coupled to said first voltage rail and providing a first voltage, second and third resistors arranged as a voltage divider between said first voltage rail and said band-gap reference voltage source, wherein a controlled output voltage for input to said second operational amplifier is taken from said voltage divider.

22. An apparatus according to claim 21, wherein:
said means for controlling further comprises a fourth resistor coupled between a third voltage rail and said gate of said representative MOS transistor.

23. An apparatus according to claim 13, wherein:
said means for controlling is located substantially on said chip.

24. An apparatus according to claim 15, wherein:
said first resistor is located off-chip.

25. An apparatus according to claim 5, further comprising:
a second representative MOS transistor of a type opposite to said representative MOS transistor, said second representative MOS transistor having a drain coupled to said current source, a source coupled to a second voltage rail, and a gate coupled to its source, said second representative MOS transistor being of said known relative first size, wherein,
said bus drivers of said plurality of output devices each have a second MOS transistor of said type opposite to said representative MOS transistor having a source coupled to said second voltage rail, a drain coupled to a respective of the plurality of threads of said data bus, and a gate coupled to said gate of said second representative MOS transistor such that each second MOS transistor, when ON, mirrors current in said second representative MOS transistor.
said second representative MOS transistor and said second MOS transistors are located on said single chip.

26. An apparatus according to claim 25, further comprising:
control means for controlling an amount of current flowing through said representative MOS transistor.

27. A system for driving an unterminated data bus, said system comprising:
a plurality of transmitters, each transmitter located
substantially on its own semiconductor chip and having
a) a current source of substantially known and stable current;
b) a representative MOS transistor having a drain coupled to said current source, a source coupled to a first voltage rail, and a gate, said representative MOS transistor being of a known relative first size;
c) at least one output device, each output device having a bus driver, and each bus driver having a first MOS transistor having a source coupled to said first voltage rail, a drain coupled to a bit of said unterminated data bus, and a gate coupled to said gate of said representative MOS transistor such that each first MOS transistor mirrors current in said
representative MOS transistor, each first MOS transistor being of a known relative second size, wherein for each transmitter, said representative MOS transistor and said at least one output device are located on a single chip, and
for each transmitter, said representative MOS transistor conducts said known and stable current from said current source, and each said bus driver, when ON, conducts a current related in size to said known and stable current as a function of said relative second size and said relative first size, such that said current related in size to said known and stable current is within a range of substantially ±20% for all transmitters for all semiconductor chips of said system.

28. A system according to claim 27, wherein:
said at least one output device comprises a plurality of output devices.

29. A method for stabilizing MOS output devices on a chip which are coupled to an unterminated data bus, comprising:
a) providing a substantially known and stable current to a representative MOS transistor on the chip, where said
representative MOS transistor is of a known relative size;
b) providing said output devices with driving transistors of substantially identical sizes which are known relative to said representative MOS transistor; and
c) arranging said output devices in current mirror
relationships with said representative MOS transistor, such that said known and stable current is mirrored in said driving transistors of said output devices when said output devices are ON to provide substantially equal driving currents which are related in size to said known and stable current.