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1. WO1996005672 - INTEGRABLE CLOCK RECOVERY CIRCUIT

Publication Number WO/1996/005672
Publication Date 22.02.1996
International Application No. PCT/DE1995/001038
International Filing Date 08.08.1995
Chapter 2 Demand Filed 07.03.1996
IPC
G06F 1/04 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
H03L 7/07 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
07using several loops, e.g. for redundant clock signal generation
H03L 7/081 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
081provided with an additional controlled phase shifter
H04L 7/00 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
H04L 7/033 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
02Speed or phase control by the received code signals, the signals containing no special synchronisation information
033using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
CPC
G06F 1/04
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
H03L 7/07
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
07using several loops, e.g. for redundant clock signal generation
H03L 7/0812
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
081provided with an additional controlled phase shifter
0812and where no voltage or current controlled oscillator is used
H04L 7/005
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
0016correction of synchronization errors
005Correction by an elastic buffer
H04L 7/0083
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
0079Receiver details
0083taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
H04L 7/0091
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
0091Transmitter details
Applicants
  • SIEMENS AKTIENGESELLSCHAFT [DE]/[DE] (AllExceptUS)
  • TRUMPP, Gerhard [DE]/[DE] (UsOnly)
Inventors
  • TRUMPP, Gerhard
Priority Data
P 44 27 972.808.08.1994DE
Publication Language German (DE)
Filing Language German (DE)
Designated States
Title
(DE) INTEGRIERBARE TAKTGEWINNUNGSSCHALTUNG
(EN) INTEGRABLE CLOCK RECOVERY CIRCUIT
(FR) CIRCUIT D'EXTRACTION DE SIGNAL D'HORLOGE POUVANT ETRE INTEGRE
Abstract
(DE)
Es wird ein Verfahren und eine vollständig integrierbare Schaltungsanordnung zur Rückgewinnung eines Taktsignales aus einem Datenstrom vorgeschlagen. Zwei Gruppen von Phasenreglern wird ein lokal vorhandenes Referenztaktsignal, bevorzugt jeweils eines von zueinander komplementären Referenztaktsignalen, zugeführt. Jeweils ein Phasenregler, der einen Zustand innerhalb seines Arbeitsbereiches eingenommen hat, wird zur Bereitstellung des zurückgewonnenen Taktsignales ausgewählt, während ein gerade nicht ausgewählter Phasenregler in einem diametralen Zustand innerhalb seines Arbeitsbereiches zu dem Zustand des gerade ausgewählten Phasenreglers bereitgehalten wird. Bei Erreichen der Grenze des Arbeitsbereiches des gerade ausgewählten Phasenreglers wird auf den bislang bereitgehaltenen Phasenregler umgeschaltet.
(EN)
A process and a fully integrable clock circuit are proposed for recovering a clock signal from a data stream. A locally available reference clock signal, preferably one of two complementary reference clock signals, is fed into each of two groups of phase regulators in each of which one phase regulator which has assumed a state within its operational range is selected for the preparation of the recovered clock signal, while a non-selected phase regulator is kept in readiness in a state within its operational range and diametrically opposite to that of the selected phase regulator. Once the limit of the operational range of the selected phase regulator is reached, a switch-over to the phase regulator which has been kept in readiness takes place.
(FR)
L'invention concerne un procédé et un circuit pouvant être entièrement intégré, servant à extraire le signal d'horloge d'un flux de données. Un signal d'horloge de référence disponible localement (de préférence l'un des signaux d'horloge de référence complémentaires) est acheminé vers deux groupes de déphaseurs. Chaque déphaseur occupant un état à l'intérieur de sa plage de fonctionnement, est sélectionné pour mettre à disposition le signal d'horloge extrait, tandis qu'un déphaseur non sélectionné est maintenu à disposition, à l'intérieur de sa plage de fonctionnement, dans un état diamétralement opposé à l'état du déphaseur sélectionné. Lorsque la plage de fonctionnement du déphaseur sélectionné atteint sa limite, on commute sur le déphaseur maintenu jusqu'alors à disposition.
Also published as
US08776695
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