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1. WO1996005656 - TIME MULTIPLEXED RATIOED LOGIC

Publication Number WO/1996/005656
Publication Date 22.02.1996
International Application No. PCT/US1995/010570
International Filing Date 17.08.1995
Chapter 2 Demand Filed 13.03.1996
IPC
H03K 19/00 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 19/017 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
01Modifications for accelerating switching
017in field-effect transistor circuits
H03K 19/096 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
08using semiconductor devices
094using field-effect transistors
096Synchronous circuits, i.e. using clock signals
H03K 19/173 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
CPC
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H03K 19/0013
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0008Arrangements for reducing power consumption
0013in field effect transistor circuits
H03K 19/01728
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
01Modifications for accelerating switching
017in field-effect transistor circuits
01728in synchronous circuits, i.e. by using clock signals
H03K 19/0963
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
08using semiconductor devices
094using field-effect transistors
096Synchronous circuits, i.e. using clock signals
0963using transistors of complementary type
H03K 19/1738
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
1733Controllable logic circuits
1738using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]
Applicants
  • LEV, Lavi, A. [IL/US]; US
Inventors
  • LEV, Lavi, A.; US
Agents
  • CAGE, Kenneth, L.; McDermott, Will & Emery Suite 450 1850 K Street, N.W. Washington, DC 20006-2296, US
Priority Data
08/292,79917.08.1994US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TIME MULTIPLEXED RATIOED LOGIC
(FR) LOGIQUE CADENCE EN MULTIPLEXAGE TEMPOREL
Abstract
(EN)
A robust family of pre-conditioned (90, 100) complementary CMOS logic elements (72) using scaled MOSFET's (86, 88) and a single clock phase (70) which may be easily interconnected to form high speed logic networks (68). The family includes both N-type and P-type pre-conditioned logic elements (90, 100) using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFET's according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.
(FR)
L'invention concerne une famille cohérente d'éléments logiques CMOS complémentaires préconditionnés (90, 100) faisant appel à des matrices MOSFET (86, 88) à synchronisation monophase (70) dont la facilité d'interconnexion permet de former des réseaux logiques à grande vitesse (68). La famille comprend à la fois des éléments logiques préconditionnés (90, 100) de type N et de type P présentant une structure CMOS à complémentarité décalée, ce qui demande peu d'énergie pour une vitesse élevée. Ces éléments logiques atteignent les niveaux de performance des CMOS de la génération à venir tout en étant fabriqués selon les procédés et avec les matériels actuels. L'invention décrit également en détail la mise en ÷uvre desdits éléments logiques. L'invention concerne également les procédés de construction matricelle desdit MOSFET. L'invention propose en outre différents procédés d'acheminement, réduisant la diaphonie d'interconnexion.
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