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1. WO1996005655 - IMPROVEMENTS IN A VLSI MEMORY CIRCUIT

Publication Number WO/1996/005655
Publication Date 22.02.1996
International Application No. PCT/US1995/010397
International Filing Date 14.08.1995
Chapter 2 Demand Filed 01.03.1996
IPC
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/22 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write timing or clocking circuits; Read-write control signal generators or management
G11C 8/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
06Address interface arrangements, e.g. address buffers
G11C 8/18 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe or column address strobe signals
CPC
G11C 7/1051
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
G11C 7/1057
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
G11C 7/106
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
106Data output latches
G11C 7/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/22
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
G11C 8/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
06Address interface arrangements, e.g. address buffers
Applicants
  • CREATIVE INTEGRATED SYSTEMS, INC. [US/US]; Suite 118 1504 Brookhollow Drive Santa Ana, CA 92705, US
  • RICOH COMPANY, LTD. [JP/JP]; 1-15-5, Minami-Aoyama Minato-ku Tokyo 107, JP
Inventors
  • KOMAREK, James, A.; US
  • PADGETT, Clarence, W.; US
  • MINNEY, Jack, L.; US
  • TANNER, Scott, B.; US
  • KOJIMA, Shin-ichi; JP
  • OISHI, Motohiro; US
  • FUKUMURA, Keiji; JP
  • NAKANISHI, Hiroaki; JP
Agents
  • DAWES, Daniel, L.; 5252 Kenilworth Drive Huntington Beach, CA 92649, US
Priority Data
08/290,54915.08.1994US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) IMPROVEMENTS IN A VLSI MEMORY CIRCUIT
(FR) AMELIORATIONS D'UN CIRCUIT MEMOIRE A TRES GRANDE ECHELLE D'INTEGRATION (VLSI)
Abstract
(EN)
The rate of increase or decrease of the rising and falling edge respectively of an output driver in a read-only memory circuit is provided by driving a CMOS output amplifier by gate control signals whose rate of increase or decrease in turn is controlled by a control signal, SLOW. The signal SLOW is generated based upon the speed of operation of the ROM and is binary, one state being indicative of normal speed of operation and a second state being indicative of a slow speed of operation of the ROM. When the signal SLOW is high, the rate at which complementary gate drive signals are applied to the CMOS amplifier are generated at a first or normal rate. However, when the signal SLOW is low, the rate of generation of these gate drive signals is also decreased to correspondingly decrease the switching speed of the CMOS amplifier. A voltage precharge signal VPC is also applied to the rate controlling circuit so that variations in the precharge voltage indicative of manufacturing parameters, voltage variations and temperature variations directly effect the rate at which the gate drive signals are generated and hence the switching speeds of the CMOS amplifier.
(FR)
La vitesse de montée du flanc avant ou la vitesse de descente du flanc arrière d'un étage de sortie d'un circuit mémoire à lecture seule est obtenue par l'excitation d'un amplificateur de sortie CMOS par des signaux de commande de grille dont la vitesse de montée ou la vitesse de descente est à son tour commandée par un signal de commande SLOW. Le signal SLOW est généré sur la base de la vitesse de fonctionnement de la mémoire ROM; il est binaire, un état étant indicatif de la vitesse normale de fonctionnement tandis que le deuxième état étant indicatif d'une vitesse lente de fonctionnement de la ROM. Lorsque le signal SLOW est élevé, la vitesse à laquelle les signaux complémentaires de commande de grille sont appliqués à l'amplificateur CMOS sont générés à une première vitesse normale. Par contre, lorsque le signal SLOW est faible, la vitesse de génération de ces signaux de commande de grille décroît elle-même pour réduire de manière correspondante la vitesse de commutation de l'amplificateur CMOS. Un signal de précharge de tension (VPC) est également appliqué au circuit de régulation de vitesse, de sorte que les variations de la tension de précharge qui sont indicatives de paramètres de production, les fluctuations de tension et les fluctuations de température influent directement sur la vitesse selon laquelle les signaux de commande de grille sont générés et, en conséquence, sur les vitesses de commutation de l'amplificateur CMOS.
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