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Machine translation
1. (WO1996005618) HIGH-VOLTAGE LDD-MOSFET WITH INCREASED BREAKDOWN VOLTAGE AND METHOD OF FABRICATION
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1996/005618    International Application No.:    PCT/US1995/010207
Publication Date: 22.02.1996 International Filing Date: 10.08.1995
IPC:
H01L 21/336 (2006.01), H01L 27/092 (2006.01), H01L 29/78 (2006.01)
Applicants: NATIONAL SEMICONDUCTOR CORPORATION [US/US]; 1090 Kifer Road, M/S 16-135, Sunnyvale, CA 95083-3737 (US)
Inventors: BERGEMONT, Albert, M.; (US)
Agent: PITRUZZELLA, Vincenzo, D.; National Semiconductor Corporation, M/S 16-135, 1090 Kifer Road, Sunnyvale, CA 94086-3737 (US)
Priority Data:
08/288,993 11.08.1994 US
Title (EN) HIGH-VOLTAGE LDD-MOSFET WITH INCREASED BREAKDOWN VOLTAGE AND METHOD OF FABRICATION
(FR) TRANSISTOR A EFFET DE CHAMP MOS, A DRAIN LEGEREMENT DOPE, A HAUTE TENSION A TENSION DE CLAQUAGE ACCRUE ET SON PROCEDE DE FABRICATION
Abstract: front page image
(EN)In a high-voltage MOS transistor that utilizes a lightly-doped drain region to isolate a heavily-doped drain region from the substrate, the reverse bias which can be applied across the drain-to-substrate junction of the transistor is increased by reducing the width of the heavily-doped drain region.
(FR)Dans un transistor MOS à tension élevée, qui utilise une zone de drain légèrement dopée pour isoler du substrat une zone de drain fortement dopée, on augmente la polarisation inverse qui peut être appliquée à travers la jonction drain-substrat du transistor en réduisant la largeur de la zone de drain fortement dopée.
Designated States: DE, KR.
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: English (EN)
Filing Language: English (EN)