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1. WO1996005613 - SEMICONDUCTOR DEVICE

Publication Number WO/1996/005613
Publication Date 22.02.1996
International Application No. PCT/JP1995/001622
International Filing Date 15.08.1995
IPC
H01L 23/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
H01L 23/498 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
CPC
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/05599
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
H01L 2224/32057
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
3205Shape
32057in side view
H01L 2224/32225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
321Disposition
32151the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
32221the body and the item being stacked
32225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/48227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
481Disposition
48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
48221the body and the item being stacked
48225the item being non-metallic, e.g. insulating substrate with or without metallisation
48227connecting the wire to a bond pad of the item
Applicants
  • CITIZEN WATCH CO., LTD. [JP/JP]; 1-1, Nishi-Shinjuku 2-chome Shinjuku-ku Tokyo 163-04, JP (AllExceptUS)
  • ISHIDA, Yoshihiro [JP/JP]; JP (UsOnly)
  • OHMORI, Yoshinobu [JP/JP]; JP (UsOnly)
  • IKEDA, Ienobu [JP/JP]; JP (UsOnly)
  • TERASHIMA, Kazuhiko [JP/JP]; JP (UsOnly)
  • TOYODA, Takeshi [JP/JP]; JP (UsOnly)
Inventors
  • ISHIDA, Yoshihiro; JP
  • OHMORI, Yoshinobu; JP
  • IKEDA, Ienobu; JP
  • TERASHIMA, Kazuhiko; JP
  • TOYODA, Takeshi; JP
Agents
  • WATANABE, Kihei ; Diamant Building, 8th floor 5, Kanda Suda-cho 1-chome Chiyoda-ku Tokyo 101, JP
Priority Data
6/19150215.08.1994JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
Abstract
(EN)
In a semiconductor device comprising an IC chip (8) mounted an a circuit substrate (7) and sealed with a molding resin (11), corner resist films (6a, 6b, 6c, 6d) are formed at positions corresponding to a corner (A) of the IC chip (8) on the circuit substrate (7), and the corner (A) of the IC chip (8) is bonded to these corner resist films by using a die bond (9). A die pattern (3a) is exposed outside the corner resist films, and a power supply pattern (3b) is so formed as to encompass their periphery. The power supply terminal, the die pattern (3a) and the power supply pattern (3b) are connected by bonding wires (10). In this way, the adhesion strength of the corner of the IC chip is improved and peel is prevented. Furthermore, bonding of a large number of bonding wires for power supply can be freely made.
(FR)
Selon la présente invention, dans un dispositif semi-conducteur à puce (8) monté sur un substrat (7) et rendu étanche par une résine moulée (11), des coins à couche de résist (6a, 6b, 6c, 6d) sont réalisés à même le substrat (7) à des emplacements correspondant à un coin (A) de puce (8), une fixation de puce permettant de fixer ledit coin (A) de puce (8) sur ces coins à couche de résist. Un tracé pour puce (3a) restant dégagé à l'extérieur des coins à couche de résist, un tracé d'alimentation électrique (3b) est réalisé de façon à englober leur périphérie. Les bornes d'alimentation électrique, les tracés de puce (3a) et leurs tracés d'alimentation électrique (3b) sont connectés par des conducteurs de métallisation (10). De cette façon, on obtient de meilleures forces d'adhésion du coin de puce, et on évite l'écaillage. En outre, on peut procéder librement à la pose d'un grands nombre de conducteurs de métallisation pour l'alimentation électrique.
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