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1. WO1996005554 - MULTIPLICATION OPERATING METHOD AND MULTIPLIER

Publication Number WO/1996/005554
Publication Date 22.02.1996
International Application No. PCT/CN1995/000064
International Filing Date 15.08.1995
Chapter 2 Demand Filed 14.03.1996
IPC
G06F 7/52 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
52Multiplying; Dividing
CPC
G06F 7/525
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
52Multiplying; Dividing
523Multiplying only
525in serial-serial fashion, i.e. both operands being entered serially
Applicants
  • DI, Zongkai [CN/CN]; CN (AllExceptUS)
  • ZHANG, Yinwei [CN/CN]; CN
Inventors
  • ZHANG, Yinwei; CN
Agents
  • NTD PATENT AND TRADEMARK AGENCY, BEIJING OFFICE; 10th floor Beisanhuanzhonglu Road 6 Dewai Beijing 100011, CN
Priority Data
94 11 4858.015.08.1994CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) MULTIPLICATION OPERATING METHOD AND MULTIPLIER
(FR) PROCEDE ET UNITE DE MULTIPLICATION
Abstract
(EN)
A multiplying method and a multiplier. Arbitrarily accurate operation can be performed on operands having arbitrary length by using the method, pair of bits each being obtained from two operands respectively are successively input from upper bit to lower bit and products output from upper bit to lower bit by way of conversion of base notation, carrying and accumulation, the operation can be stopped at any bit so that arbitrary accuracy can be selected for the products, the method is suitable for the multi-stage parallel consecutive multiplication. The multiplier is substantially composed of register, control logic circuit, quinary conversion circuit, carry decode circuit, unit circuit, buffer, accumulator and product register stack, conventional floating and fixed point multiplier and divider may be replaced by the multiplier, with the problem that multiplier is limited by wordlength and has low calculation speed being resolved.
(FR)
Une opération arbitrairement exacte peut être effectuée sur des opérandes de longueur arbitraire à l'aide du procédé, chaque paire de bits obtenue à partir de deux opérandes est successivement introduite du bit supérieur au bit inférieur et les produits sont sortis du bit supérieur au bit inférieur par conversion de la notation de base, report et cumul, l'opération peut être arrêtée au niveau de n'importe quel bit de sorte que l'exactitude arbitraire peut être choisie pour les produits. Ce procédé convient pour la multiplication consécutive parallèle multi-étage. L'unité de multiplication comporte un registre, un circuit logique de commande, un circuit de conversion quinaire, un circuit de décodage de report, un circuit périphérique, un tampon, une pile de registres de cumul et de produit; l'unité de multiplication et l'unité de division classiques en virgule flottante et en virgule fixe peuvent être remplacées par l'unité de multiplication, celle-ci n'étant plus limitée par la longueur de mot et sa faible vitesse de calcul.
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