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1. WO1996003700 - ARRANGEMENT AT AN IMAGE PROCESSOR

Publication Number WO/1996/003700
Publication Date 08.02.1996
International Application No. PCT/SE1995/000868
International Filing Date 18.07.1995
Chapter 2 Demand Filed 07.02.1996
IPC
G06F 15/80 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06T 1/20 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
20Processor architectures; Processor configuration, e.g. pipelining
CPC
G06F 15/8015
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
80comprising an array of processing units with common control, e.g. single instruction multiple data processors
8007single instruction multiple data [SIMD] multiprocessors
8015One dimensional arrays, e.g. rings, linear arrays, buses
G06T 1/20
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
20Processor architectures; Processor configuration, e.g. pipelining
Applicants
  • IVP INTEGRATED VISION PRODUCTS AB [SE/SE]; Teknikringen 2C S-583 30 Linköping, SE (AllExceptUS)
  • FORCHHEIMER, Robert [SE/SE]; SE (UsOnly)
  • ÅSTRÖM, Anders [SE/SE]; SE (UsOnly)
Inventors
  • FORCHHEIMER, Robert; SE
  • ÅSTRÖM, Anders; SE
Agents
  • WILLQUIST, Bo ; Albihn Willquist AB S:t Larsgatan 23 S-582 24 Linköping, SE
Priority Data
9402551-722.07.1994SE
Publication Language English (EN)
Filing Language Swedish (SV)
Designated States
Title
(EN) ARRANGEMENT AT AN IMAGE PROCESSOR
(FR) AGENCEMENT DE PROCESSEUR D'IMAGE
Abstract
(EN)
The present invention relates to a parallel processor containing a number of processor elements of the same type which are integrated on one and the same semiconductor chip. The processor is of the type that allows image and signal processing of the information stored in the processor element. The device contains a unit block (3) for each processor element and is characterised in that each unit block comprises at least two incrementing units (1a, 1b) which are designed to add a signal supplied to the unit block and a signal which originates from an incrementing unit corresponding to the respective unit in the closest preceding unit block in every direction of the processor element matrix. Every unit block (3) further contains at least one logical unit (2) which is designed to perform Boolean logic operations on the signals received from the incrementing units of the unit block.
(FR)
Cette invention se rapporte à un processeur parallèle contenant un certain nombre d'éléments processeurs du même type, lesquels sont intégrés sur une seule et même puce de semi-conducteur. Ce processeur est de type permettant un traitement des images et des signaux relatifs aux informations stockées dans les éléments processeurs. Ledit dispositif contient un bloc unitaire (3) pour chaque élément processeur et se caractérise en ce que chaque bloc unitaire comprend au moins deux unités incrémentielles (1a, 1b), lesquelles sont conçues pour additionner un signal fourni au bloc unitaire et un signal qui est généré par une unité incrémentielle correspondant à l'unité respective se trouvant dans le bloc unitaire précédent le plus proche dans chaque direction de la matrice des éléments processeurs. Chaque bloc unitaire (3) comprend en outre au moins une unité logique (2), qui est conçue pour effectuer des opérations de logique booléenne sur les signaux reçus en provenance des unités incrémentielles du bloc unitaire.
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