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1. WO1996002916 - MEMORY WITH STRESS CIRCUITRY FOR DETECTING DEFECTS

Publication Number WO/1996/002916
Publication Date 01.02.1996
International Application No. PCT/US1995/007745
International Filing Date 16.06.1995
Chapter 2 Demand Filed 23.01.1996
IPC
G11C 29/50 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
50Marginal testing, e.g. race, voltage or current testing
CPC
G11C 11/41
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
G11C 29/50
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
50Marginal testing, e.g. race, voltage or current testing
G11C 29/50016
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
50Marginal testing, e.g. race, voltage or current testing
50016of retention
Applicants
  • INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95052, US
Inventors
  • ROSEN, Eitan; IL
  • MILSTAIN, Yakov; IL
Agents
  • MALLIE, Michael, J. ; Blakely, Sokoloff, Taylor & Zafman 7th floor 12400 Wilshire Boulevard Los Angeles, CA 90025-1026, US
Priority Data
08/277,14819.07.1994US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY WITH STRESS CIRCUITRY FOR DETECTING DEFECTS
(FR) MEMOIRE COMPORTANT UN CIRCUIT DE CONTRAINTE SERVANT A DETECTER DES DEFAUTS
Abstract
(EN)
A memory circuit (20) is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit (20) comprises a memory cell array (22) coupled to bit lines, an access circuit (24) coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells.
(FR)
L'invention concerne un circuit de mémoire (20) comportant un circuit de contrainte servant à détecter des défauts de retenue de données dans les cellules de mémoire. Ce circuit de mémoire (20) comprend un ensemble de cellules de mémoire (22) couplées à des lignes de bits, un circuit d'accès (24) couplé, afin d'accéder aux cellules de mémoire, ainsi qu'un circuit de décharge couplé, afin d'exercer une contrainte sur les cellules de mémoire.
Latest bibliographic data on file with the International Bureau