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1. WO1995034030 - FLASH MEMORY BASED MAIN MEMORY

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[ EN ]

CLAIMS
What is claimed is:
1. A computer system comprising:
a microprocessor;
a high speed bus;
a nonvolatile main memory, the non-volatile main memory providing first data to the microprocessor through the high speed bus.

2. The computer system as set forth in claim 1, wherein the non-volatile main memory provides the first data to the
microprocessor through the high speed bus with zero microprocessor wait states.
3. The computer system as set forth in claim 1, wherein the nonvolatile main memory is flash memory.
4. The computer system as set forth in claim 1, wherein the high speed bus is a synchronous bus.
5. The computer system as set forth in claim 1, wherein the high speed bus is an asynchronous bus.
6. The computer system as set forth in claim 1, wherein the high speed bus is a local bus.
7. The computer system as set forth in claim 1, wherein the high speed bus is a main memory bus.
8. The computer system as set forth in claim 1, wherein the first data includes program instructions to be executed by the microprocessor.
9. The computer system as set forth in claim 1, wherein the microprocessor has an internal cache, the internal cache storing data for use by the microprocessor.
10. The computer system as set forth in claim 1, wherein the microprocessor is a static microprocessor.
11. The computer system as set forth in claim 1, wherein the nonvolatile main memory can be placed into an energy saving deep powerdown state.

12. The computer system as set forth in claim 11, wherein the microprocessor can order the nonvolatile memory to enter and to leave the deep powerdown state.
13. The computer system as set forth in claim 1, further comprising a volatile main memory, the volatile main memory providing second data to the microprocessor through the high speed bus.
14. The computer system as set forth in claim 13, wherein the second data includes program instructions to be executed by the microprocessor.
15. The computer system as set forth in claim 13, wherein the volatile main memory is battery backed.
16. The computer system as set forth in claim 13, wherein the volatile main memory is static random access memory.
17. The computer system as set forth in claim 13, wherein the volatile main memory is dynamic random access memory.
18. The computer system as set forth in claim 13, wherein the volatile main memory operates as a write cache for third data to be stored in the nonvolatile main memory.
19. The computer system as set forth in claim 13, wherein the volatile main memory operates as an external cache for the first data stored in the nonvolatile main memory.
20. The computer system as set forth in claim 1, wherein the computer system further comprises nonvolatile store memory coupled to the nonvolatile main memory.
21. The computer system as set forth in claim 1, wherein the computer system further comprises:
a low speed bus;
a bus bridge coupling the high and low speed buses; and
a nonvolatile store memory coupled to the low speed bus.
22. The computer system as set forth in claim 1, wherein the first data has a first part and a second part, the nonvolatile main memory further comprising: a plurality of nonvolatile memory units, the plurality of nonvolatile memory units including first and second memory units, the first part of the first data being stored in the first nonvolatile memory unit and the second part of the first data being stored in the second nonvolatile memory unit;
an interlace control unit, the interlace control unit controlling access by the microprocessor to the plurality of nonvolatile memory units, if the first data is to be provided to the microprocessor, the interlace controller causing the first nonvolatile memory unit to provide the first part of the first data to the microprocessor and the interlace controller causing the second nonvolatile memory unit to begin retrieving the second part of the first data while the first nonvolatile memory unit is providing the first part of the first data to the microprocessor, the interlace controller then causing the second nonvolatile memory unit to provide the second part of the first data to the microprocessor after the first nonvolatile memory unit has provided the first part of the first data to the microprocessor.
23. The computer system as set forth in claim 22, further comprising a clock, the clock providing a clock signal to the interlace controller, the interlace controller causing the first nonvolatile memory unit to provide the first part of the first data to the
microprocessor on a first pulse of the clock and the interlace controller causing the second nonvolatile memory unit to provide the second part of the first data to the microprocessor on a second pulse of the clock.
24. The computer system as set forth in claim 23, wherein the first part of the first data has an associated first address and the microprocessor requests that the first data be provided to the microprocessor by providing the first address to the interlace controller on a third pulse of the clock, the third pulse occurring before the first and second pulses of the clock.
25. The computer system as set forth in claim 24, wherein an address latch enable signal is provided to the interlace controller on the third pulse to indicate that the first address is being provided to the interlace controller.
26. The computer system as set forth in claim 24 wherein the second part of the first data has an associated second address and the interlace controller calculates the second address based upon the first address.
27. The computer system as set forth in claim 26, wherein the interlace controller calculates the second address by incrementing the first address by a predetermined amount.
28. The computer system as set forth in claim 27, wherein the predetermined amount is one.
29. The computer system as set forth in claim 26, wherein the interlace controller calculates the second address by decrementing the first address by a predetermined amount.
30. The computer system as set forth in claim 29, wherein the predetermined amount is one.
31. The computer system as set forth in claim 24, wherein the second part of the first data has an associated second address and a request that the second part of the first data be provided to the microprocessor is made by providing the second address to the interlace controller on a fourth pulse of the clock, the fourth pulse occurring after the third pulse of the clock.
32. The computer system as set forth in claim 31, wherein an address latch enable signal is provided to the interlace controller on the fourth pulse to indicate that the second address is being provided to the interlace controller.
33. The computer system as set forth in claim 22, wherein the first and second parts of the first data belong to a single cache line.
34. The computer system as set forth in claim 22, wherein the first nonvolatile memory unit is a first integrated circuit and the second nonvolatile memory units is a second integrated circuit.
35. The computer system as set forth in claim 34, wherein the interlace controller is a third integrated circuit.

36. The computer system as set forth in claim 22, wherein the first and second nonvolatile memory units are separate banks of a first integrated circuit.
37. The computer system as set forth in claim 36, wherein the interlace controller is a second integrated circuit.
38. The computer system as set forth in claim 36, wherein the interlace controller is part of the first integrated circuit.
39. The computer system as set forth in claim 22, wherein the first part of the first data has an associated first row address and first column address and wherein the microprocessor initiates access to the first part of the first data by providing the first row and column addresses to the interlace controller.
40. The computer system as set forth in claim 39, wherein the first row address is provided during a row address strobe pulse and the first column address is provided during a column address strobe pulse.
41. The computer system as set forth in claim 39, wherein the second part of the first data has an associated second row address and second column address and wherein the microprocessor initiates access to the second part of the first data by providing the second row and column addresses to the interlace controller.
42. The computer system as set forth in claim 41, wherein the second row address is provided during a row address strobe pulse and the second column address is provided during a column address strobe pulse.
43. The computer system as set forth in claim 22, wherein the first data has an associated row address and column address and wherein the microprocessor initiates access to the first data by providing the row and column addresses to the nonvolatile main memory.
44. The computer system as set forth in claim 43, wherein the row address is provided during a row address strobe pulse and the column address is provided during a column address strobe pulse.
45. A memory device comprising: a plurality of nonvolatile memory banks including first and second banks;
an interlace controller, the interlace controller controlling access to the plurality of nonvolatile memory banks, the interlace controller causing the first bank to provide first data and causing the second bank to begin retrieving second data while the first bank is providing the first data, the interlace controller then causing the second bank to provide the second data after the first bank has provided the first data.
46. The memory device as set forth in claim 45, wherein a clock signal is provided to the interlace controller, the interlace controller causing the first bank to provide the first data on a first pulse of the clock and the interlace controller causing the second bank to provide the second data on a second pulse of the clock.
47. The memory device as set forth in claim 46, wherein the first data has an associated first address specified to the interlace controller on a third pulse of the clock, the third pulse occurring before the first and second pulses of the clock.
48. The memory device as set forth in claim 47, wherein an address latch enable signal is provided to the interlace controller on the third pulse to indicate that the first address is being provided to the interlace controller.
49. The memory device as set forth in claim 47 wherein the second data has an associated second address and the interlace controller calculates the second address based upon the first address.

50. The memory device as set forth in claim 49, wherein the interlace controller calculates the second address by incrementing the first address by a predetermined amount.
51. The memory device as set forth in claim 50, wherein the predetermined amount is one.
52. The memory device as set forth in claim 49, wherein the interlace controller calculates the second address by decrementing the first address by a predetermined amount.

53. The memory device as set forth in claim 52, wherein the predetermined amount is one.
54. The memory device as set forth in claim 47, wherein the second data has an associated second address specified to the interlace controller on a fourth pulse of the clock, the fourth pulse occurring after the third pulse of the clock.
55. The memory device as set forth in claim 54, wherein an address latch enable signal is provided to the interlace controller on the fourth pulse to indicate that the second address is being provided to the interlace controller.
56. The memory device as set forth in claim 45, wherein the first and second data belong to a single cache line.
57. The memory device as set forth in claim 45, wherein the interlace controller can enter a noninterlace mode, when in the noninterlace mode, the interlace controller will not permit a second access to the plurality of nonvolatile memory banks to begin until a first access to the plurality of nonvolatile memory banks has completed.
58. The memory device as set forth in claim 57, wherein the interlace controller can enter an address multiplexing mode, when in the address multiplexing mode, a particular portion of one of the plurality of nonvolatile memory banks is specified to the interlace controller by a row and column address pair.
59. The memory device as set forth in claim 58, wherein the row address is provided during a row address strobe pulse and the column address is provided during a column address strobe pulse.
60. The memory device as set forth in claim 58, wherein the interlace controller combines the row and column address pair to form a bank address, the interlace controller then uses the bank address to specify the particular portion of one of the plurality of nonvolatile memory banks to access.
61. The memory device as set forth in claim 58, wherein the first data has an associated first row address and first column address pair and wherein the interlace controller initiates access to the first data upon receiving the first row and column addresses.
62. The memory device as set forth in claim 61, wherein the first row address is received during a row address strobe pulse and the first column address is received during a column address strobe pulse.

63. The memory device as set forth in claim 61, wherein the interlace controller combines the first row and column address pair to form a first bank address, the interlace controller then uses the bank address to specify that the first data of the first bank is to be accessed.
64. The memory device as set forth in claim 61, wherein the second data has an associated second row address and second column address pair and wherein the interlace controller initiates access to the second data by upon receiving the second row and column addresses.

65. The memory device as set forth in claim 64, wherein the second row address is received during a row address strobe pulse and the second column address is received during a column address strobe pulse.
66. The memory device as set forth in claim 65, wherein the interlace controller combines the second row and column address pair to form a second bank address, the interlace controller then uses the second bank address to specify the second data of the second bank is to be accessed.
67. The memory device as set forth in claim 45, wherein the interlace controller can enter an address multiplexing mode, when in the address multiplexing mode, a particular portion of one of the plurality of nonvolatile memory banks is specified to the interlace controller by a row and column address pair.
68. The memory device as set forth in claim 67, wherein the row address is provided during a row address strobe pulse and the column address is provided during a column address strobe pulse.
69. The memory device as set forth in claim 68, wherein the interlace controller combines the row and column address pair to form a bank address, the interlace controller then uses the bank address to specify the particular portion of one of the plurality of nonvolatile memory banks to access.
70. The memory device as set forth in claim 45, wherein the first data is identified by a first address and wherein the memory device further comprises a first address latch, the interlace controller controlling the first address latch and causing the first address latch to latch the first address prior to the interlace controller causing the first bank to provide the first data.
71. The memory device as set forth in claim 70, wherein the second data is identified by a second address and wherein the memory device further comprises a second address latch, the interlace controller controlling the second address latch and causing the second address latch to latch the second address prior to the interlace controller causing the second bank to provide the second data.
72. The memory device as set forth in claim 45, wherein the first data is identified by a first address and wherein the interlace controller further comprises an address transition detector, when the address transition detector detects an address transition to an address of the first bank, the interlace controller causes the first bank to prepare to provide data.
73. The memory device as set forth in claim 72, wherein the second data is identified by a second address and wherein when the address transition detector detects an address transition to an address of the second bank, the interlace controller causes the second bank to prepare to provide data.
74. The memory device as set forth in claim 45, further comprising:
an output buffer, the output buffer storing output data; and a bank selector, the bank selector selecting the first bank to provide to the output buffer the first data as the output data when the first bank is providing the first data and the bank selector selecting the second bank to provide to the output buffer the second data as the output data when the second bank is providing the second data.

75. The memory device as set forth in claim 45,' further comprising bus specific logic, the bus specific logic receiving bus specific input signals and providing bus specific output signals in response.
76. The memory device as set forth in claim 45, further comprising a parity generator, the parity generator generating a parity signal based upon the first data when the first data is provided.
77. The memory device as set forth in claim 45, wherein the parity generator generates a parity signal based upon the second data when the second data is provided.
78. The memory device as set forth in claim 45, wherein at least one of the plurality of nonvolatile memory banks is comprised of flash memory.
79. A memory device, comprising:
a nonvolatile memory bank;
an address demultiplexer, the address demultiplexer receiving a multiplexed row and column address pair and combining the row and column address to form a bank address, the bank address being used to access the memory bank.
80. The memory device as set forth in claim 79, wherein the nonvolatile memory bank is a flash memory bank.
81. The memory device as set forth in claim 79, wherein the nonvolatile memory bank is a flash memory and the memory device emulates a dynamic random access memory (DRAM) device.
82. The memory device as set forth in claim 79, wherein the address demultiplexer comprises:
an address latch, the address latch having a row address latch and a column address latch;
an address multiplexer, when the address multiplexer receives the row address, the address multiplexer provides the row address to the row address latch to be latched therein, when the address multiplexer receives the column address, the address multiplexer provides the column address to the column address latch to be latched therein;

once the row and column addresses have been latched in the address latch, the address latch provides the row and column addresses to the memory bank as the bank address used to access the memory bank.
83. The memory device as set forth in claim 79, wherein the row address is provided during a row address strobe pulse and the column address is provided during a column address strobe pulse.
84. The memory device as set forth in claim 83, wherein the address demultiplexer comprises:
an address latch, the address latch having a row address latch and a column address latch;
an address multiplexer, during the row address strobe pulse, the address multiplexer receives the row address and provides the row address to the row address latch to be latched therein, and during the column address strobe pulse, the address multiplexer receives the column address and provides the column address to the column address latch to be latched therein;
once the row and column addresses have been latched in the address latch, the address latch provides the row and column addresses to the memory bank as the bank address used to access the memory bank.
85. The memory device as set forth in claim 79, wherein the address demultiplexer can enter a nonmultiplexed addressing mode, when in the nonmultiplexed addressing mode, the address
demultiplexer receives a bank address and uses the bank address to access the memory bank.
86. The memory device as set forth in claim 79, wherein the nonvolatile memory bank does not require refreshing and wherein the address demultiplexer further comprises a refresh cycle detector to detect a refresh cycle.
87. The memory device as set forth in claim 86, wherein the memory device further comprises a tri-statable latch coupled to the memory bank and to the refresh cycle detector, the latch adapted to hold data for an access to the memory bank, and further wherein if the refresh cycle detector detects a refresh cycle, the refresh cycle detector causes the latch to tri-state during the refresh cycle.
88. A memory sub-system comprising:
at least two nonvolatile memory devices, each memory device for storing a corresponding portion of a page of data;
an interlace controller coupled to the nonvolatile memory devices and controlling an interlaced read of the page of data, if the interlace controller detects a read operation to the page, the interlace controller enables the memory devices and causes each memory device to read the corresponding portion of the page, the interlace controller then sequentially enabling each memory device to output the corresponding portion of the page.
89. The memory sub-system as set forth in claim 88 wherein each memory device is a flash memory device.
90. The memory sub-system as set forth in claim 88, wherein there are a plurality of pages of data including a first and second page and wherein the interlace controller further comprises a page transition detector to detect a transition from a read operation for the first page to a read operation for the second page and if the transition is detected, the page transition detector causes the interlace controller to control the reading of the second page from the memory devices.
91. The memory sub-system as set forth in claim 90, wherein the page transition detector detects every page transition from one page of the plurality of pages to another page of the plurality of pages and if the transition is detected, the page transition detector causes the interlace controller to control the reading from the memory devices of the page to which the transition was made.
92. The memory sub-system as set forth in claim 88, wherein the interlace controller receives a clock signal comprising a series of clock pulses and wherein the interlace controller sequentially enables each memory device to output the corresponding portion of the page during a different one of the pulses of the clock signal.
93. The memory sub-system as set forth in claim 92, wherein each of the portions of the page has a corresponding address, wherein the interlace controller receives a different address of the
corresponding addresses during a corresponding different one of the clock cycles and wherein the interlace controller then causes the each of the portions of the page to be output in the order in which the addresses were received.
94. The memory sub-system as set forth in claim 93, wherein the interlace controller receives an address latch enable pulse when the different address of the corresponding addresses is to be received.

95. The memory sub-system as set forth in claim 93, wherein if the interlace controller does not receive addresses for every portion of the page, the interlace controller will only cause the portions of the page to be read that correspond to the addresses received.
96. A system comprising:
a high speed synchronous bus having a data burst access bus protocol;
a nonvolatile memory device having at least two banks of nonvolatile memory and a generic interlace controller to control interlaced accesses to the banks according to a generic data burst access memory protocol;
a glue logic device coupled between the high speed
synchronous bus and the nonvolatile memory device, the glue logic receiving the burst access bus protocol from the high speed bus of a burst access to the nonvolatile memory, converting the burst access bus protocol from the high speed bus to the generic data burst access memory protocol, and then providing the converted generic data burst access memory protocol to the memory device.
97. The system as set forth in claim 96, wherein at least one of the banks of nonvolatile memory is flash memory.
98. The system as set forth in claim 96, wherein the data burst access bus protocol uses a linear addressing sequence.
99. The system as set forth in claim 96, wherein the data burst access bus protocol uses a non-linear addressing sequence.
100. The system as set forth in claim 96, wherein the glue logic device further comprising bus specific logic, the bus specific logic receiving bus specific input signals from the bus and providing bus specific output signals to the bus in response.
101. The system as set forth in claim 96, further comprising a parity generator, the parity generator generating a parity signal based upon the data burst being accessed.
102. A memory module comprising:
a nonvolatile memory;
a memory module board upon which the nonvolatile memory is mounted, the memory module board, if the memory module board provides the nonvolatile memory with a multiplexed row and column address pair indicating a memory location within the nonvolatile memory to be accessed, the nonvolatile memory accessing the memory location indicated.
103. The memory module set forth in claim 102, wherein the nonvolatile memory is comprised of at least one flash memory device.
104. The memory module as set forth in claim 102, wherein the nonvolatile memory emulates dynamic random access memory.
105. The memory module as set forth in claim 102, wherein the nonvolatile memory emulates asynchronous dynamic random access memory.
106. The memory module as set forth in claim 102, wherein the nonvolatile memory emulates synchronous dynamic random access memory.
107. The memory module as set forth in claim 102, further comprising a voltage converter coupled to the nonvolatile memory and to the memory module board, the voltage converter converting an operating voltage from the memory module board into a
programming voltage and providing the programming voltage to the nonvolatile memory.
108. The memory module as set forth in claim 107, wherein the nonvolatile memory can be disabled and wherein the memory module further comprises a programming voltage monitor coupled to the nonvolatile memory and to the voltage converter, the voltage monitor monitoring the programming voltage from the voltage converter programming voltage and if the programming voltage provided to the nonvolatile memory is not within a predetermined voltage range, the voltage monitor disabling the nonvolatile memory.

109. The memory module as set forth in claim 108, wherein the nonvolatile memory is disabled by entering a deep powerdown mode.

110. The memory module as set forth in claim 102, wherein the memory module is a single in-line memory module.
111. A system comprising:
a nonvolatile memory module having a nonvolatile memory device that emulates a dynamic random access memory (DRAM) device; and
a DRAM controller, coupled to the nonvolatile memory module and controlling access to the nonvolatile memory module.
112. The system as set forth in claim 111, wherein the
nonvolatile memory device is a flash memory device.
113. The system as set forth in claim 111, wherein the
nonvolatile memory module comprises a plurality of nonvolatile memory devices.
114. The system as set forth in claim 111, wherein the
nonvolatile memory device emulates an asynchronous DRAM device.
115. The system as set forth in claim 111, wherein the
nonvolatile memory device emulates a synchronous DRAM device.
116. The system of claim 111, further comprising a volatile memory module having a volatile memory device, the volatile memory module coupled to, and controlled by, the DRAM controller.

117. The system as set forth in claim 111, further comprising a high speed bus, coupled to the DRAM controller and indicating to the DRAM controller the accesses to the nonvolatile memory to be controlled by the DRAM controller.
118. The system as set forth in claim 117, wherein the high speed bus is an asynchronous bus.

119. The system as set forth in claim 117, wherein the high speed bus is a synchronous bus.
120. The system as set forth in claim 117, wherein the high speed bus is a main memory bus.
121. The system as set forth in claim 117, wherein the high speed bus is a local bus.
122. The system as set forth in claim 117, further comprising a memory cache coupled to the high speed local bus.
123. The system as set forth in claim 117, further comprising a microprocessor coupled to the high speed local bus.
124. A method of accessing a nonvolatile memory device, the method comprising the steps of:
providing a first address to the memory device, the first address specifying a first location within the nonvolatile memory device to be read;
receiving a series of output data from the memory device, the output data from the series of output data including first data stored at the first address.
125. The method as set forth in claim 124, further comprising the step of:
providing a clock signal comprising a series of output clock pulses to the memory device, each output clock pulse signifying to the memory device when a different one of the series of output data is to be received from the memory device.
126. The method as set forth in claim 125, further comprising the step of:
providing an address latch signal to the memory device when the first address is provided to the memory device to indicate to the memory device that the first address is being provided.
127. The method as set forth in claim 124, further comprising the steps of: providing a clock signal to the memory device, the clock signal comprising a series of address input clock pulses followed by a series of output clock pulses, each input clock pulse of the series of input clock pulses being provided with a corresponding address specifying a location in the memory device to be read, each output clock pulse signifying to the memory device when a different one of the series of output data is to be received from the memory device.
128. The method as set forth in claim 127, further comprising the steps of:
providing an address latch signal to the memory device with each address input clock pulse of the series of address input clock pulses to indicate to the memory device that the address
corresponding to the input clock pulse is being provided.
129. The method as set forth in claim 124, wherein the step of providing the first address to the memory device further comprises the steps of:
providing a row address to the memory device;
providing a column address to the memory device, the row and column address together indicating the first address to the memory device.
130. The method as set forth in claim 129, further comprising the step of:
providing a row address strobe to the memory device when providing the row address to the memory device, to indicate to the memory device that the row address is being provided.
131. The method as set forth in claim 130, further comprising the step of:
providing a column address strobe to the memory device when providing the column address to the memory device, to indicate to the memory device that the column address is being provided.
132. The method as set forth in claim 129, further comprising the step of:
prior to providing the row address strobe to the memory device, indicating to the memory device that the memory device is to enter a multiplexed address mode.
133. The method as set forth in claim 124, further comprising the step of: prior to providing the first address to the memory device, indicating to the memory device that the memory device is to enter a synchronous address mode.
134. A method of accessing a nonvolatile memory device, comprising the steps of:
providing a row address to the memory device;
providing a column address to the memory device;
receiving output data from the memory device, the output data being contents stored by the memory device at a location
corresponding to the row and column address provided to the memory device.
135. The method as set forth in claim 134, further comprising the step of providing a row address strobe to the memory device when the row address is provided to the memory device to indicate that the row address is being provided.
136. The method as set forth in claim 134, further comprising the step of providing a column address strobe to the memory device when the column address is provided to the memory device to indicate that the column address is being provided.
137. The method as set forth in claim 134, further comprising the step of:
receiving a series of additional output data from the memory device, the additional output data from the series of output data being received after the output data corresponding to the row and column address provided to the device.
138. The method as set forth in claim 137, further comprising the step of:
providing a clock signal comprising a series of output clock pulses to the memory device, each output clock pulse signifying to the memory device when a different one of the series of output data is to be received from the memory device.
139. The method as set forth in claim 138, further comprising the step of: prior to providing the row address to the memory device, indicating to the memory device that the memory device is to enter a synchronous address mode.