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1. WO1995034030 - FLASH MEMORY BASED MAIN MEMORY

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Publication Number WO/1995/034030
Publication Date 14.12.1995
International Application No. PCT/US1995/007062
International Filing Date 01.06.1995
Chapter 2 Demand Filed 19.12.1995
IPC
G06F 12/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 12/0607
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
0607Interleaved addressing
G06F 12/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 2212/2022
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
20Employing a main memory using a specific memory technology
202Non-volatile memory
2022Flash memory
G11C 7/1045
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1015Read-write modes for single port memories, i.e. having either a random port or a serial port
1045Read-write mode select circuits
G11C 7/1072
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1072for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Y02D 10/00
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
10Energy efficient computing, e.g. low power processors, power management or thermal management
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • MILLS, Duane, R.
  • DIPERT, Brian, Lyn
  • SAMBANDAN, Sachidanandan
  • MCCORMICK, Bruce
  • PASHLEY, Richard, D.
Agents
  • TAYLOR, Edwin, H.
Priority Data
08/253,49903.06.1994US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FLASH MEMORY BASED MAIN MEMORY
(FR) MEMOIRE CENTRALE S'ARTICULANT AUTOUR D'UNE MEMOIRE FLASH
Abstract
(EN)
A flash memory chip (320) that can be switched into four different read modes is described. Computer systems (100, 200, 300, 800, 1300, 1500) and hierarchies that exploit these modes are also described. In the first read mode, asynchronous flash mode, the flash memory (130) is read as a standard flash memory. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip (320) and a series of addresses belonging to a data burst are specified, one address per clock tick. In the third read mode, asynchronous DRAM (dynamic random access memory) mode, the flash memory (130) emulates DRAM. In the fourth read mode, synchronous DRAM mode, the features of the second and third modes are combined to yield a flash memory that emulates a synchronous DRAM.
(FR)
Cette invention se rapporte à une puce de mémoire flash (320) qui peut être commutée en quatre modes de lecture différents. Des systèmes d'ordinateurs (100, 200, 300, 800, 1300, 1500) et les hiérarchies qui exploitent ces modes sont également décrits. Dans le premier mode de lecture, à savoir le mode flash asynchrone, la mémoire flash (130) est lue comme une mémoire flash standard. Dans le deuxième mode de lecture, à savoir le mode flash synchrone, un signal d'horloge est fourni à la puce flash (320) et une série d'adresses appartenant à une salve de données est spécifiée, à raison d'une adresse par top d'horloge. Dans le troisième mode de lecture, à savoir un mode DRAM (mémoire à accès sélectif dynamique), la mémoire flash (130) sert à émuler la mémoire DRAM. Dans le quatrième mode de lecture, à savoir le mode DRAM synchrone, les caractéristiques du deuxième et du troisième mode sont combinées pour produire une mémoire flash permettant d'émuler une mémoire DRAM synchrone.
Also published as
AU1995027658
CN1155341
CN1430151
EP0765498
KR1002814320000*
SG34685
US5696917
US6026465
US6385688
US6564285
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