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Machine translation
1. (WO1994016461) CMOS LOCOS ISOLATION FOR SELF-ALIGNED NPN BJT IN A BICMOS PROCESS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1994/016461    International Application No.:    PCT/US1993/012632
Publication Date: 21.07.1994 International Filing Date: 27.12.1993
Chapter 2 Demand Filed:    10.05.1994    
IPC:
H01L 21/762 (2006.01), H01L 21/8249 (2006.01)
Applicants: VLSI TECHNOLOGY, INC. [US/US]; 1109 McKay Drive, San Jose, CA 95131 (US)
Inventors: CHANG, Kuang-Yeh; (US).
WEI, Yi-Hen; (US)
Agent: KREBS, Robert, E.; Burns, Doane, Swecker & Mathis, George Mason Building, Washington & Prince Streets, P.O. Box 1404, Alexandria, VA 22313-1404 (US)
Priority Data:
08/000,433 04.01.1993 US
Title (EN) CMOS LOCOS ISOLATION FOR SELF-ALIGNED NPN BJT IN A BICMOS PROCESS
(FR) ISOLATION PAR LA TECHNIQUE CMOS LOCMOS DE TRANSISTORS BIPOLAIRES A JONCTIONS NPN A GRILLE AUTO-ALIGNEE DANS UN PROCEDE BiCMOS
Abstract: front page image
(EN)A method of fabricating BiCMOS devices, and the resultant BiCMOS devices are disclosed. According to the present invention, over-etching to the substrate (2) on the deposited polysilicon emitter (25) is prevented by providing additional oxide (22) beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an endpoint during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT (self-aligned transistor) masking and oxidation steps.
(FR)L'invention se rapporte à un procédé de fabrication de dispositifs BiCMOS et aux dispositifs BiCMOS obtenus. Selon la présente invention, la mise en place d'oxyde supplémentaire (22) sous une couche de polysilicium servant d'arrêt au réactif d'attaque empêche la surattaque du substrat (2) sur l'émetteur (25) de polysilicium. Malgré l'inclusion d'un oxyde pour former un point limite lors de la configuration d'un émetteur, on réduit la complexité de fabrication en évitant les étapes de masquage et d'oxydation du transistor supplémentaire à grille auto-alignée (SAT).
Designated States: JP, KR.
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE).
Publication Language: English (EN)
Filing Language: English (EN)