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1. (WO1994000875) SEMICONDUCTOR STORAGE ARRANGEMENT AND PROCESS FOR PRODUCING IT

Pub. No.:    WO/1994/000875    International Application No.:    PCT/DE1993/000552
Publication Date: Jan 6, 1994 International Filing Date: Jun 24, 1993
IPC: H01L 21/8242
H01L 27/108
Applicants: SIEMENS AKTIENGESELLSCHAFT
KÜSTERS, Karl, Heinz
STELZ, Franz, Xaver
MÜLLER, Wolfgang
Inventors: KÜSTERS, Karl, Heinz
STELZ, Franz, Xaver
MÜLLER, Wolfgang
Title: SEMICONDUCTOR STORAGE ARRANGEMENT AND PROCESS FOR PRODUCING IT
Abstract:
The storage arrangement has DRAM storage cells in which the capacitor is arranged above the transistor and above the bit line (stacked capacitor above bit line cell). According to the invention, the cell essentially has self-adjusting contact holes for the connection of a capacitor plate (19, 33, 40) and the bit line (16) to the transistor (45). Thereby, and through the planarisation before the contact holes (12, 13) are made, the bit line (16) can be produced on a reltively flat surface. The capacitor may be a flat type or, to increase the capacitance, take the form of a dish or comb-shaped capacitor. The storage matrix of the invention with corrugated word lines reinforces planarisation and minimises the space required.