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1. WO1992016945 - SEMICONDUCTOR MEMORY

Publication Number WO/1992/016945
Publication Date 01.10.1992
International Application No. PCT/JP1992/000327
International Filing Date 18.03.1992
IPC
A61M 29/02 2006.01
AHUMAN NECESSITIES
61MEDICAL OR VETERINARY SCIENCE; HYGIENE
MDEVICES FOR INTRODUCING MEDIA INTO, OR ONTO, THE BODY; DEVICES FOR TRANSDUCING BODY MEDIA OR FOR TAKING MEDIA FROM THE BODY; DEVICES FOR PRODUCING OR ENDING SLEEP OR STUPOR
29Dilators with or without means for introducing media, e.g. remedies
02Inflatable dilators; Dilators made of swellable materials
A61N 1/32 2006.01
AHUMAN NECESSITIES
61MEDICAL OR VETERINARY SCIENCE; HYGIENE
NELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
1Electrotherapy; Circuits therefor
18Applying electric currents by contact electrodes
32alternating or intermittent currents
G11C 11/419 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417for memory cells of the field-effect type
419Read-write circuits
CPC
A61N 1/325
AHUMAN NECESSITIES
61MEDICAL OR VETERINARY SCIENCE; HYGIENE
NELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
1Electrotherapy; Circuits therefor
18Applying electric currents by contact electrodes
32alternating or intermittent currents
325for iontophoresis, i.e. transfer of media in ionic state by an electromotoric force into the body
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
419Read-write [R-W] circuits
Applicants
  • FUJITSU LIMITED [JP]/[JP] (AllExceptUS)
  • FUKUSHI, Isao [JP]/[JP] (UsOnly)
Inventors
  • FUKUSHI, Isao
Agents
  • ITOH, Tadahiko
Priority Data
3/5747520.03.1991JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR MEMORY
(FR) MEMOIRE A SEMI-CONDUCTEUR
Abstract
(EN)
A semiconductor memory comprising a pair of write means (4a and 4b) for bringing either of a pair of bit lines (25a and 25b) into a low potential (24) depending on a write signal, and a read means for detecting the data in either of the memory cells (11 and 11') through the bit lines (25a and 25b) in response to a read signal. The read means includes a pair of bipolar transistors (41a and 41b), of which collectors are connected to a high-potential power source (22) through a load means (42a and 42b) and emitters are connected to the bit lines (25a and 25b). A pair of gate circuits (43a and 44a) and (43b and 44b) operate selectively to turn on one of the bipolar transistors (41a and 41b) by applying the high potential of the power source (22) to the base of one bipolar transistor (41a or 41b) in response to the read signal when reading data and turn off the bipolar transistors (41a and 41b) by applying a high potential to the base of the other bipolar transistor depending on the write signal when writing data. Differential amplifiers (5a and 5b) detect the potential difference between inputs because inputs are connected to collectors of a pair of transistors (41a and 41b) respectively.
(FR)
Mémoire à semi-conducteur comprenant une paire de moyens d'écriture (4a et 4b) destinée à amener l'une ou l'autre d'une paire de lignes binaires (25a et 25b) à un faible potentiel (24) en fonction d'un signal d'écriture, ainsi qu'un moyen de lecture destiné à détecter les données se trouvant dans l'une ou l'autre des cellules de mémoire (11 et 11') par les lignes binaires (25a et 25b) en réponse à un signal de lecture. Le moyen de lecture comprend une paire de transistors bipolaires (41a et 41b) dont les collecteurs sont connectés à une source d'alimentation à potentiel élevé (22) par un moyen de charge (42a et 42b), et des émetteurs sont connectés aux lignes binaires (25a et 25b). Une paire de circuits-porte (43a et 44a) et (43b et 44b) mettent sélectivement en circuit un des transistors bipolaires (41a et 41b) par application du potentiel élevé de la source d'alimentation (22) à la base d'un transistor bipolaire (41a ou 41b), en réponse au signal de lecture lors de la lecture de données, et ils mettent hors circuit les transistors bipolaires (41a et 41b) par application d'un potentiel élevé à la base de l'autre transistor bipolaire en fonction du signal d'écriture lors de l'écriture de données. Des amplificateurs différentiels (5a et 5b) détectent la différence de potentiel entre les entrées puisque lesdites entrées sont connectées à des collecteurs d'une paire de transistors (41a et 41b) respectivement.
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