Processing

Please wait...

Settings

Settings

Goto Application

1. WO1992016053 - PROGRAMMABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT AND LOGIC CELL THEREFOR

Publication Number WO/1992/016053
Publication Date 17.09.1992
International Application No. PCT/US1992/001765
International Filing Date 02.03.1992
Chapter 2 Demand Filed 02.10.1992
IPC
H03K 19/173 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
H03K 19/177 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
CPC
H03K 19/1737
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
1733Controllable logic circuits
1737using multiplexers
H03K 19/17704
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17704the logic functions being realised by the interconnection of rows and columns
H03K 19/17728
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17724Structural details of logic blocks
17728Reconfigurable logic blocks, e.g. lookup tables
H03K 19/17736
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17736Structural details of routing resources
H03K 19/1774
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17736Structural details of routing resources
1774for global signals, e.g. clock, reset
H03K 19/1778
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
1778Structural details for adapting physical parameters
Applicants
  • QUICKLOGIC CORPORATION [US]/[US]
Inventors
  • CHAN, Andrew, K.
  • BIRKNER, John, M.
  • CHUA, Hua-Thye
Agents
  • CARROLL, David, H.
  • WINTERS, Paul, J.
Priority Data
665,10306.03.1991US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PROGRAMMABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT AND LOGIC CELL THEREFOR
(FR) CIRCUIT INTEGRE PROGRAMMABLE A SPECIFICITE D'APPLICATION ET CELLULE LOGIQUE ASSOCIEE
Abstract
(EN)
A field programmable gate array includes a programmable routing network (82, 84, 90, 92, 94, 96), a programmable configuration network (80) integrated with the programmable routing network; and a logic cell (100) integrated with the programmable configuration network. The logic cell includes four two-input AND gates (104, 106, 108, 110), two six-input AND gates (102, 112), three multiplexers (114, 116, 118), and a delay flipflop (120). The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
(FR)
L'invention se rapporte à une matrice de portes programmable par l'utilisateur, qui comprend un réseau d'acheminement programmable (82, 84, 90, 92, 94, 96), un réseau de configuration programmable (80) intégré au réseau d'acheminement programmable, et une cellule logique (100) intégrée au réseau de configuration programmable. La cellule logique contient quatre portes ET à deux entrées (104, 106, 108, 110), deux portes ET à six entrées (102, 112), trois multiplexeurs (MUX) (114, 116, 118), et une bascule à retard (120). La cellule logique constitue un bloc fonctionnel logique universel puissant et d'usage général destiné à permettre la réalisation de la plupart des fonctions de logique transistor-transistor et de macrobibliothèque à matrice de portes. Une varitété considérable de fonctions est réalisable avec un seul retard de cellule, tel que des fonctions de logique combinatoire aussi étendues que treize entrées, toutes les fonctions de tansfert booléen concernant jusqu'à trois entrées et les fonctions de bascules séquentielles telles que bascule T, bascule JK et bascule de comptage avec report.
Latest bibliographic data on file with the International Bureau