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1. WO1992015061 - SYSTEM FOR DISTRIBUTED MULTIPROCESSOR COMMUNICATION

Publication Number WO/1992/015061
Publication Date 03.09.1992
International Application No. PCT/US1991/008793
International Filing Date 22.11.1991
Chapter 2 Demand Filed 01.09.1992
IPC
G06F 9/46 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
G06F 15/167 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
167using a common memory, e.g. mailbox
CPC
G06F 15/167
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
167using a common memory, e.g. mailbox
G06F 9/52
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
G06F 9/526
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
526Mutual exclusion algorithms
Applicants
  • CRAY RESEARCH, INC. [US]/[US]
Inventors
  • SCHIFFLEGER, Alan, J.
Agents
  • HAMRE, Curtis, B.
Priority Data
655,29614.02.1991US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM FOR DISTRIBUTED MULTIPROCESSOR COMMUNICATION
(FR) SYSTEME DE COMMUNICATION REPARTIE DE MULTIPROCESSEUR
Abstract
(EN)
A tightly coupled communication scheme based on a common shared resource circuit and adapted particularly to a multiprocessing system including 2N CPUs. A mechanism has been added that allows data in a shared register to be read and incremented as a single instruction, eliminating the need for semaphore manipulations during the operation. A second mechanism has been added to permit the use of indirect addressing in the addressing of semaphore bits and shared registers. Operating systems can relocate semaphore bits and message areas to permit simultaneous execution of the same function within a single task. In addition, an instruction has been added which tests of the semaphore bit and acts upon the state of that bit. If the semaphore bit is not set then the processor takes control of the semaphore bit by setting it. If the semaphore bit is set, the processor will execute a branch and execute other instructions. Thus, jobs assigned to a processor in a multiprocessing, multitasking application do not block or wait for the semaphore bit to clear.
(FR)
Système de communication à couplage étroit basé sur un circuit de partage de ressources commun et particulièrement adapté à un système à multiprocesseur comprenant 2N unités centrales. Un mécanisme a été ajouté, lequel permet à des données d'un registre partagé d'être lues et incrémentées sous forme d'une instruction unique, ce qui rend inutiles des manipulations de sémaphore au cours du fonctionnement. Un second mécanisme a été ajouté afin de permettre l'utilisation d'un adressage indirect lors de l'adressage de bits de sémaphore et de registres partagés. Les systèmes d'exploitation peuvent transférer des bits de sémaphore et des zones de message afin de permettre l'exécution simultanée de la même fonction au cours d'une tâche unique. En outre, l'on a ajouté une instruction qui teste le bit de sémaphore et agit sur l'état de ce bit. Si le bit de sémaphore n'est pas mis à 1, le processeur assume le contrôle du bit de sémaphore et le met à 1. Si ce bit est déjà mis à 1, le processeur va exécuter un branchement ainsi que d'autres instructions. Ainsi, les tâches affectées à un processeur dans une application multitâche, multiprocesseur, ne se bloquent pas et ne doivent pas attendre que le bit de sémaphore soit remis à zéro.
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