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1. (WO1992010802) METHOD AND APPARATUS FOR MULTIPROCESSOR DIGITAL COMMUNICATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1992/010802 International Application No.: PCT/US1991/009237
Publication Date: 25.06.1992 International Filing Date: 09.12.1991
Chapter 2 Demand Filed: 23.06.1992
IPC:
G06F 13/12 (2006.01) ,G06F 15/17 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
10
Programme control for peripheral devices
12
using hardware independent of the central processor, e.g. channel or peripheral processor
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
16
Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
163
Interprocessor communication
17
using an input/output type connection, e.g. channel, I/O port
Applicants:
STREAM COMPUTERS, INC. [US/US]; 337 Calcaterra Court Palo Alto, CA 94306, US
Inventors:
SCHWEDE, Gary, W.; US
Agent:
YIN, Ronald, L. ; Limbach & Limbach 2001 Ferry Building San Francisco, CA 94111, US
Priority Data:
627,63914.12.1990US
Title (EN) METHOD AND APPARATUS FOR MULTIPROCESSOR DIGITAL COMMUNICATION
(FR) PROCEDE ET APPAREIL DE TRANSMISSION NUMERIQUE ENTRE PLUSIEURS PROCESSEURS
Abstract:
(EN) In the present invention a digital communication controller (20) for interfacing with a master processor (12) and a synchronous bus (14) having a plurality of slave processors (18a, ..., 18n) connected thereto is disclosed. The digital communication controller (20) provides synchronous transfer of instruction and data in each microcycle to the bus (14). However, the data provided in each microcycle is multiplexed such that it is associated with the instruction transmitted previously but not contiguous in time therewith.
(FR) Cette invetnion concerne un système de commande de transmission numérique (20) permettant de relier un processeur maître (12) à un bus synchrone (14) comprenant plusieurs processeurs asservis (18a, ..., 18n) connectés à ce dernier. Le système de commande de transmission numérique (20) assure le transfert synchrone des instructions et des données de chaque microcycle, vers le bus (14). Cependant, les données dans chaque microcycle sont multiplexées de sorte qu'elles sont associées à l'instruction préalablement transmise mais sans présenter de contiguïté temporelle avec elle.
Designated States: AU, CA, JP
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, MC, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0562022JPH06503669AU1991091558