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1. (WO1991018447) BASIC CELL FOR BiCMOS GATE ARRAY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/018447 International Application No.: PCT/US1991/003191
Publication Date: 28.11.1991 International Filing Date: 08.05.1991
Chapter 2 Demand Filed: 12.12.1991
IPC:
H01L 27/118 (2006.01) ,H03K 19/0944 (2006.01) ,H03K 19/173 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
118
Masterslice integrated circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
08
using semiconductor devices
094
using field-effect transistors
0944
using MOSFET
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
173
using elementary logic circuits as components
Applicants:
SiARC [US/US]; 1485 Hamilton Avenue Palo Alto, CA 94301, US
Inventors:
EL GAMAL, Abbas; US
Agent:
OGONOWSKY, Brian, D. ; Skjerven, Morrill, MacPherson, Franklin & Friel 25 Metro Drive Suite 700 San Jose, CA 95110, US
Priority Data:
524,18315.05.1990US
Title (EN) BASIC CELL FOR BiCMOS GATE ARRAY
(FR) CELLULE DE BASE POUR RESEAU DE PORTES BiCMOS
Abstract:
(EN) An improved cell (20) for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P (44 and 46) and N-channel (50 and 52), two small N-channel transistors (54 and 56), and a single small P-channel transistor (48). Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor (58), a large N-channel pull-down transistor (62), and a small P-channel transistor (60). By using this cell, an extremely high compute capability per die area is achieved.
(FR) Une cellule améliorée (20) destinée à être utilisée dans un réseau de portes à programmation par masque est décrite. La cellule préférée comprend deux sections de calcul qui comprennent chacune deux paires de transistors de taille moyenne à canaux P (44 et 46) et N (50 et 52), deux petits transistors à canal N (54 et 56), et un seul petit transistor à canal P (48). Chaque cellule contient aussi une section de commande de haute efficacité comportant un seul transistor bipolaire de tirage vers le haut (58), un grand transistor de tirage vers le bas à canal N (62) et un petit transistor à canal P (60). L'utilisation de cette cellule permet d'obtenir une capacité de calcul extrêmement élevée par zone de matrice.
Designated States: AT, AU, BB, BG, BR, CA, CH, DE, DK, ES, FI, GB, HU, JP, KP, KR, LK, LU, MC, MG, MW, NL, NO, PL, RO, SD, SE, SU
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, ML, MR, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0528956JPH06501813KR1002172100000*AU1991078991