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1. (WO1991018416) INTERDIGITATED TRANS-DIE LEAD CONSTRUCTION AND METHOD OF CONSTRUCTION FOR MAXIMIZING POPULATION DENSITY OF CHIP-ON-BOARD CONSTRUCTION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/018416 International Application No.: PCT/US1991/003403
Publication Date: 28.11.1991 International Filing Date: 14.05.1991
Chapter 2 Demand Filed: 06.12.1991
IPC:
H01L 21/60 (2006.01) ,H01L 23/495 (2006.01) ,H01L 23/498 (2006.01) ,H05K 1/18 (2006.01) ,H05K 3/34 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
495
Lead-frames
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
18
Printed circuits structurally associated with non-printed electric components
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
34
by soldering
Applicants:
SCHENDELMAN, Richard, Lee [US/US]; US
Inventors:
SCHENDELMAN, Richard, Lee; US
Agent:
LYON, Robert, E. ; 611 West Sixth Street 34th Floor Los Angeles, CA 90017, US
Priority Data:
522,94714.05.1990US
522,95014.05.1990US
Title (EN) INTERDIGITATED TRANS-DIE LEAD CONSTRUCTION AND METHOD OF CONSTRUCTION FOR MAXIMIZING POPULATION DENSITY OF CHIP-ON-BOARD CONSTRUCTION
(FR) STRUCTURE DE FILS INTERDIGITES TRANS-PUCE ET PROCEDE DE REALISATION MAXIMALISANT LA DENSITE DE POPULATION DANS UNE STRUCTURE DE PUCE SUR PLAQUETTE
Abstract:
(EN) A novel implementation of a tape automated bonding process of attaching leads (44) to a semiconductor die (50) is disclosed which utilizes a method of attaching tape leads which extend across the interior surface of the die (50) rather than radially outwardly from the die (50). Two-layer or three-layer tape construction is used, with the insulation (30A) being located between the top of the die (50) and the leads (44). This technique enables lead placement on opposite sides of the die (50) in interdigitated fashion, allowing die (50) to be installed on a circuit board (70) more closely adjacent than has previously been possible.
(FR) Nouveau mode de réalisation d'un procédé de bondérisation automatique à film consistant à fixer des fils (44) à une puce semi-conductrice (50), utilisant un procédé de fixation de fils s'étendant sur la surface intérieure de la puce (50) et non radialement vers l'extérieur à partir de la puce (50). On utilise une structure de film à deux ou à trois couches, l'isolation (30A) se trouvant entre la partie supérieure de la puce (50) et les fils (44). Cette technique permet de placer des fils sur les côtés opposés de la puce (50) de manière interdigitée, ce qui offre la possibilité d'installer la puce (50) sur une carte de circuit (70) plus étroitement adjacente qu'auparavant.
Designated States: AU, BR, CA, FI, JP, KR, NO, PL, RO
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
AU1991079544