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1. (WO1991018351) PYRAMID LEARNING ARCHITECTURE NEUROCOMPUTER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/018351 International Application No.: PCT/US1991/003317
Publication Date: 28.11.1991 International Filing Date: 17.05.1991
IPC:
G06N 3/063 (2006.01) ,G06N 3/10 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
06
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063
using electronic means
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
10
Simulation on general purpose computers
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; Old Orchard Road Armonk, NY 10504, US
Inventors:
PECHANEK, Gerald, George; US
VASSILIADIS, Stamatis; US
DELGADO-FRIAS, Jose, Guadalupe; US
Agent:
CRANE, John, D.; International Business Machines Corporation 1701 North Street IP Law Department - N50 251/2 Endicott, NY 13760, US
Priority Data:
526,86622.05.1990US
682,78608.04.1991US
Title (EN) PYRAMID LEARNING ARCHITECTURE NEUROCOMPUTER
(FR) ORDINATEUR NEURONAL A ARCHITECTURE D'APPRENTISSAGE PYRAMIDALE
Abstract:
(EN) The Pyramid Learning Architecture Neurocomputer (PLAN) (Figures 1 and 2) is a scalable stacked pyramid arrangement of processor arrays. There are six processing levels (Figures 1 and 2) in PLAN consisting of the pyramid base, level 6, containing N2 SYnapse Processors (SYPs), level 5 containing multiple folded Communicating Adder Tree structures (SCATs), level 4 made up of N completely connected Neuron Execution Processors (NEPs) (Fig. 16) level 3 made up of multiple Programmable Communicating Alu Tree (PCATs) structures, (Figures 12 and 13) similar to level 5 SCATs but with programmable function capabilities in each tree node, level 2 containing the Neuron Instruction Processor (NIP), and level 1 comprising the host and user interface. The simplest processors are in the base level with each layer of processors increasing in computational power up to a general purpose host computer acting as the user interface. PLAN is scalable in direct neural network emulation and in virtual processing capability.
(FR) L'ordinateur neuronal à architecture d'apprentissage pyramidale (PLAN) est un agencement pyramidal empilé et évolutif de rangs de processeurs. Il existe six niveaux de traitement dans le PLAN, c'est-à-dire la base de la pyramide, le niveau 6, comportant N2 processeurs synaptiques (SYP), le niveau 5 comportant de multiples structures pliées d'arbres additionneurs communicants (SCAT), le niveau 4 comportant N processeurs d'exécution neuronale (NEP) entièrement connectés, le niveau 3 comportant de multiples structures d'arbres Alu communicants et programmables (PCAT) qui sont différents des SCAT du niveau 5 en ce qu'ils ont des capacités de fonctions programmables dans chaque n÷ud d'arbre, le niveau 2 comportant le processeur d'instruction neuronal (NIP), et enfin le niveau 1 comportant les interfaces hôte et utilisateur. Les processeurs les plus simples se trouvent dans le niveau de base, et la puissance de calcul des processeurs s'accroît de niveau en niveau jusqu'à un ordinateur hôte polyvalent servant d'interface utilisateur. Le PLAN est évolutif en ce qui concerne l'émulation directe du réseau neuronal et la capacité de traitement virtuel.
Designated States: JP
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0484522