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1. (WO1991018347) SPIN: A SEQUENTIAL PIPELINED NEUROCOMPUTER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/018347 International Application No.: PCT/US1991/002251
Publication Date: 28.11.1991 International Filing Date: 08.04.1991
IPC:
G06N 3/063 (2006.01) ,G06N 3/10 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
06
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063
using electronic means
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
10
Simulation on general purpose computers
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; Old Orchard Road Armonk, NY 10504, US
Inventors:
VASSILIADIS, Stamatis; US
PECHANEK, Gerald, George; US
DELGADO-FRIAS, Jose, Guadalupe; US
Agent:
CRANE, John, D.; International Business Machines Corp. 1701 North Street IP Law Department - N50 251/2 Endicott, NY 13760, US
Priority Data:
526,86622.05.1990US
Title (EN) SPIN: A SEQUENTIAL PIPELINED NEUROCOMPUTER
(FR) NEURO-ORDINATEUR A TRAITEMENT 'PIPELINE' SEQUENTIEL
Abstract:
(EN) The neural computing paradigm is characterized as dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neuron processing elements. This discussion proposes a neural network architecture called SPIN, a Sequential Pipelined Neurocomputer (Figure 2). The SPIN processor (Figure 2) models neural networks producing high performance with minimum hardware by sequentially processing each neuron in the modeled completely connected network with a pipelined physical neuron structure. Various versions of the SPIN processor are examined and their performance is evaluated and compared to the ring systolic array neural network architecture.
(FR) Le paradigme de traitement neural est caractérisé en ce qu'il représente un système dynamique, hautement parallèle et à calcul intensif typiquement composé de multiplications pondérales d'entrée, de totalisation de produits, de calculs d'états neuraux, et d'une entière connectivité entre les éléments de traitement de neurones. Cette invention propose une architecture à réseau neural appelée SPIN, ou Neuro-ordinateur à Traitement 'Pipeline' Séquentiel (Figure 2). Le processeur SPIN (Figure 2) crée des modèles de réseaux neuraux à performances élevées et utilisant un minimum de matériel, en traitant de manière séquentielle chaque neurone dans le réseau de modèle entièrement connecté, avec une structure à neurone physique et traitée 'pipeline'. De différentes versions du processeur SPIN sont examinées et leurs performances évaluées et comparées à l'architecture à réseau neural et à alignement systolique en anneau.
Designated States: JP
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0484507