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1. (WO1991017605) FRACTIONAL N/M SYNTHESIS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/017605 International Application No.: PCT/US1991/002743
Publication Date: 14.11.1991 International Filing Date: 22.04.1991
IPC:
H03L 7/183 (2006.01) ,H03L 7/197 (2006.01) ,H03L 7/20 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18
using a frequency divider or counter in the loop
183
a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18
using a frequency divider or counter in the loop
197
a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
20
using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it
Applicants:
MOTOROLA, INC. [US/US]; 1303 East Algonquin Road Schaumburg, IL 60196, US
Inventors:
BLACK, Gregory, R.; US
HIETALA, Alexander, W.; US
Agent:
PARMELEE, Steven, G. ; Motorola, Inc. Intellectual Property Dept. 1303 East Algonquin Road Schaumburg, IL 60196, US
Priority Data:
516,89730.04.1990US
Title (EN) FRACTIONAL N/M SYNTHESIS
(FR) SYNTHESE FRACTIONNAIRE DE TYPE N/M
Abstract:
(EN) A frequency synthesizer employs a frequency divider (103) and a frequency multiplier (403) in the feedback loop. The minimum frequency separation between two adjacent synthesized channels is equal to the reference frequency divided by the multiplication ratio of the multiplier. The division ratio of the frequency divider (103), which can be analyzed as the sum of an integer and a fractional portion, is varied with time by a digital sequence, resulting in a minimum frequency increment equal to a fraction of the reference frequency. The multiplier (403) acts to reduce the nonlinearities of the frequency synthesizer when the fractional portion of the division ratio causes a large variation in the instantaneous division ratio by reducing the effective division ratio of the loop.
(FR) Un synthétiseur de fréquence utilise un démultiplicateur de fréquence (103) et un multiplicateur de fréquence (403) dans la boucle de réaction. La séparation de fréquence minimale entre deux canaux synthétisés contigus est égale à la fréquence de référence divisée par le rapport de multiplication du multiplicateur. Le rapport de division du démultiplicateur de fréquence (103), qui peut être analysé comme étant la somme d'un nombre entier et d'une partie fractionnaire, est modifié dans le temps par une séquence numérique, ce qui se traduit par un incrément de fréquence minimal égal à une fraction de la fréquence de référence. Le multiplicateur (403) sert à réduire les non-linéarités du synthétiseur de fréquence lorsque la partie fractionnaire du rapport de division entraîne une variation importante du rapport de division instantané, en réduisant le rapport de division effectif de la boucle.
Designated States: AU, BR, CA, JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0480018CA2048646AU1991078581