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1. (WO1991017604) MULTIACCUMULATOR SIGMA-DELTA FRACTIONAL-N SYNTHESIS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/017604 International Application No.: PCT/US1991/002742
Publication Date: 14.11.1991 International Filing Date: 22.04.1991
IPC:
H03C 3/09 (2006.01) ,H03L 7/197 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
C
MODULATION
3
Angle modulation
02
Details
09
Modifications of modulator for regulating the mean frequency
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18
using a frequency divider or counter in the loop
197
a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
Applicants:
MOTOROLA, INC. [US/US]; 1303 East Algonquin Road Schaumburg, IL 60196, US
Inventors:
HIETALA, Alexander, W.; US
RABE, Duane, C.; US
Agent:
PARMELEE, Steven, G. ; Motorola, Inc. Intellectual Property Dept. 1303 East Algonquin Road Schaumburg, IL 60196, US
Priority Data:
516,99330.04.1990US
Title (EN) MULTIACCUMULATOR SIGMA-DELTA FRACTIONAL-N SYNTHESIS
(FR) SYNTHESE FRACTIONNAIRE DE TYPE N A MODULATEUR SIGMA-DELTA ET A ACCUMULATEURS MULTIPLES
Abstract:
(EN) A fractional-N synthesizer (803) employing at least a second order sigma-delta modulator (900) is disclosed. The most significant bits from the output accumulator (1011) of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider (103). Modulation to the synthesizer is introduced as part of the digital number input to sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.
(FR) Un synthétiseur fractionnaire de type N (803) utilisant au moins un modulateur (900) sigma-delta de deuxième ordre est décrit. Les binaires les plus significatifs de l'accumulateur de sortie (1011) du modulateur sigma-delta sont utilisés comme commande d'exécution pour le diviseur variable du démultiplicateur à boucle (103). Le signal de modulation envoyé au synthétiseur fait partie de l'entrée numérique d'un chiffre dans le modulateur sigma-delta et la production de signaux parasites est réduite au moyen de la sélection d'un chiffre élevé comme dénominateur de la partie fractionnaire du diviseur du démultiplicateur à boucle.
Designated States: AU, BR, CA, JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0480012CA2048645AU1991077970