Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO1991017506) APPARATUS AND METHOD FOR CONTROLLING DATA FLOW BETWEEN A COMPUTER AND MEMORY DEVICES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/017506 International Application No.: PCT/US1991/002314
Publication Date: 14.11.1991 International Filing Date: 03.04.1991
Chapter 2 Demand Filed: 06.11.1991
IPC:
G06F 11/00 (2006.01) ,G06F 11/10 (2006.01) ,G06F 11/20 (2006.01) ,G11B 20/18 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
08
Error detection or correction by redundancy in data representation, e.g. by using checking codes
10
Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
16
Error detection or correction of the data by redundancy in hardware
20
using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G PHYSICS
11
INFORMATION STORAGE
B
INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
20
Signal processing not specific to the method of recording or reproducing; Circuits therefor
10
Digital recording or reproducing
18
Error detection or correction; Testing
Applicants:
SF2 CORPORATION [US/US]; 140 Kifer Court Sunnyvale, CA 94086, US
Inventors:
POWERS, David, T.; US
JAFFE, David, H.; US
HENSON, Larry, P.; US
JOHNSON, Hoke, S., III; US
GLIDER, Joseph, S.; US
IDLEMAN, Thomas, E.; US
Agent:
HAUGHEY, Paul, C.; Townsend and Townsend One Market Plaza 2000 Steuart Tower San Francisco, CA 94105, US
Priority Data:
506,70306.04.1990US
Title (EN) APPARATUS AND METHOD FOR CONTROLLING DATA FLOW BETWEEN A COMPUTER AND MEMORY DEVICES
(FR) DISPOSITIF ET PROCEDE DE REGULATION D'UN FLUX DE DONNEES ENTRE UN ORDINATEUR ET DES MEMOIRES PERIPHERIQUES
Abstract:
(EN) A method and apparatus for controlling data flow between a computer (10) and a group of memory devices (18A...18M) arranged in a particular logical configuration. The system includes a group of first level controllers (12A, 12B) and a group of second level controllers (14A, 14B). The first level controllers (12A, 12B) and the second level controllers (14A, 14B) work together such that if one of the second level controllers (14a, 14B) fails, the routing between the first level controllers (12A, 12B) and the memory devices (18A...18M) is switched to a properly functioning second level controller (14A, 14B) without the need to involve the computer (10) in the rerouting process. The logical configuration of the memory devices (18A...18M) remains constant. The invention also includes switching circuitry (16A1...16M6) which permits a functioning second level controller (14A, 14B) to assume control of a group of memory devices (18A...18M) formerly controlled by the failed second level controller (14A, 14B).
(FR) Procédé et dispositif de régulation d'un flux de données entre un ordinateur (10) et un groupe de mémoires périphériques (18A...18M) disposées selon une configuration logique particulière. Le système comprend un groupe d'unités de contrôle du premier niveau (12A, 12B) et un groupe d'unités de contrôle du deuxième niveau (14A, 14B). L'un (12A, 12B) et l'autre (14A, 14B) de ces groupes travaillent ensemble, de sorte qu'en cas de défaillance de l'une des unités de contrôle du deuxième niveau (14a, 14B), l'acheminement entre les unités de contrôle du premier niveau (12A, 12B) et les mémoires périphériques (18A...18M) est commuté sur une unité du deuxième niveau (14A, 14B) fonctionnant normalement sans que l'ordinateur (10) n'ait à intervenir dans cette procédure de réacheminement. La configuration logique des mémoires périphériques (18A...18M) reste constante. L'invention comporte aussi un ensemble de circuits (16A1...16M6) permettant à une unité de contrôle du deuxième niveau (14A, 14B) fonctionnant normalement de prendre le contrôle d'un groupe de mémoires périphériques (18A...18M) qui étaient antérieurement commandées par l'unité défaillante du deuxième niveau (14A, 14B).
Designated States: AT, AU, BB, BG, BR, CA, CH, DE, DK, ES, FI, GB, HU, JP, KP, KR, LK, LU, MC, MG, MW, NL, NO, RO, SD, SE, SU
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
African Intellectual Property Organization (BF, BJ, CF, CG, CM, GA, ML, MR, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0524247AU1991076886