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1. (WO1991009480) SYNCHRONOUS-ASYNCHRONOUS CONVERTER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/009480 International Application No.: PCT/FR1990/000897
Publication Date: 27.06.1991 International Filing Date: 10.12.1990
IPC:
H04J 3/16 (2006.01) ,H04J 3/06 (2006.01) ,H04L 12/64 (2006.01) ,H04L 7/00 (2006.01) ,H04Q 11/04 (2006.01) ,H04Q 3/52 (2006.01) ,H04L 12/70 (2013.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
J
MULTIPLEX COMMUNICATION
3
Time-division multiplex systems
16
in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
J
MULTIPLEX COMMUNICATION
3
Time-division multiplex systems
02
Details
06
Synchronising arrangements
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12
Data switching networks
64
Hybrid switching systems
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
Q
SELECTING
11
Selecting arrangements for multiplex systems
04
for time-division multiplexing
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
Q
SELECTING
3
Selecting arrangements
42
Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
52
using static devices in switching stages, e.g. electronic switching arrangements
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12
Data switching networks
70
Packet switching systems
Applicants:
ALCATEL N.V. [NL/NL]; Strawinskylaan 341 NL-1077 XX Amsterdam, NL
Inventors:
BALZANO, Jean-Michel; FR
LE BOUFFANT, Alain; FR
Agent:
POTHET, Jean ; SOSPI 14-16, rue de la Baume F-75008 Paris, FR
Priority Data:
89/1649713.12.1989FR
Title (EN) SYNCHRONOUS-ASYNCHRONOUS CONVERTER
(FR) CONVERTISSEUR SYNCHRONE-ASYNCHRONE
Abstract:
(EN) The converter is comprised of a memory (SRAM) having a first port and a second port, a managing circuit for the first port (SPM) connected to the first port, to an incoming synchronous multiplex line (ME) and to an outgoing synchronous multiplex line (MS), and a circuit for managing the second port (APM) connected to the second port, to an incoming asynchronous link (LE) through a FIFO type cell memory (M), and to an outgoing asynchronous link (LS). A control unit (MF) external to the converter, and applied to the port managing circuits, allows to choose the mode of operation of the converter; in a first mode (M32), each time interval of a raster of a synchronous multiplex is affected to communication channel, and in a second mode (M1) all time intervals of a synchronous raster are affected to a channel.
(FR) Le convertisseur comprend une mémoire (SRAM) ayant un premier et un deuxième port, un circuit de gestion du premier port (SPM) relié au premier port, à une ligne multiplex synchrone entrante (ME) et à une ligne multiplex synchrone sortante (MS), et un circuit de gestion du deuxième port (APM) relié au deuxième port, à une liaison asynchrone entrante (LE) par l'intermédiaire d'une mémoire cellules (M) de type FIFO, et à une liaison asynchrone sortante (LS). Une commande (MF) extérieure au convertisseur, et appliquée aux circuits de gestion des ports permet de choisir le mode de fonctionnement du convertisseur; dans un premier mode (M32) chaque intervalle temporel d'une trame d'un multiplex synchrone est affecté à un canal de communication et dans un deuxième mode (M1) tous les intervalles temporels d'une trame synchrone sont affectés à un canal.
Designated States: AU, JP, KR, SU
Publication Language: French (FR)
Filing Language: French (FR)
Also published as:
ES2081958EP0433154RU02097929JP3084058JPH04504641DE000069024928
AU1991069102FR2655794