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1. (WO1991009423) IMPROVED REDUCED CAPACITANCE CHIP CARRIER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/009423 International Application No.: PCT/US1990/007097
Publication Date: 27.06.1991 International Filing Date: 04.12.1990
IPC:
H01L 23/13 (2006.01) ,H01L 23/14 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
CRAY RESEARCH, INC. [US/US]; 608 Second Avenue South Minneapolis, MN 55402, US
Inventors:
EBERLEIN, Delvin, D.; US
Agent:
HAMRE, Curtis, B.; Merchant, Gould, Smith, Edell, Welter & Schmidt 3100 Norwest Center 90 South Seventh Street Minneapolis, MN 55402, US
Priority Data:
447,65108.12.1989US
Title (EN) IMPROVED REDUCED CAPACITANCE CHIP CARRIER
(FR) BOITIER A PUCES AMELIORE A CAPACITANCE REDUITE
Abstract:
(EN) An integrated circuit chip carrier having reduced and predictable interlead capacitance, reduced glass chip formation, and improved wirebonding characteristics is disclosed. The chip carrier includes a substrate (201) having a central cavity (106) for locating an integrated circuit die, an inner channel (202) and an outer channel (203), adhesive glass (105) located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads (107) embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass (104) extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.
(FR) On décrit un boîtier à puces pour circuits intégrés possédant une capacitance réduite et prévisible entre les fils conducteurs, une formation réduite de fragments de verre et des caractéristiques de liaison câblée améliorés. Le boîtier à puces comprend un substrat (201) possèdant un orifice central (106) pour accueillir une matrice de circuit intégré, un canal interne (202) et un canal externe (203), du verre adhésif (105) implanté dans les canaux et débordant au-dessus de la surface du substrat, et comporte une pluralité de fils (107) implantés dans le verre adhésif débordant et prenant appui de manière coplanaire sur le substrat, lesdits fils se prolongeant au-delà de la périphérie du substrat vers l'intérieur près du bord de l'orifice, et une fine couche de verre de scellement (104) dépassant la périphérie du substrat par-dessus le canal externe de façon à rendre totalement étanche le boîtier à puces.
Designated States: CA, JP, KR
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)