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1. (WO1991008591) SEPARATION OF DIODE ARRAY CHIPS DURING FABRICATION THEREOF
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/008591 International Application No.: PCT/US1990/006489
Publication Date: 13.06.1991 International Filing Date: 14.11.1990
IPC:
H01L 21/301 (2006.01) ,H01L 21/304 (2006.01) ,H01L 27/15 (2006.01) ,H01L 33/00 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
15
including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
Applicants:
EASTMAN KODAK COMPANY [US/US]; 343 State Street Rochester, NY 14650, US
Inventors:
McCLURG, Scott, Douglas; US
Agent:
RUSHEFSKY, Norman; 343 State Street Rochester, NY 14650-2201, US
Priority Data:
439,91921.11.1989US
Title (EN) SEPARATION OF DIODE ARRAY CHIPS DURING FABRICATION THEREOF
(FR) SEPARATION DES PUCES DES RESEAUX DE DIODES AU COURS DE LEUR FABRICATION
Abstract:
(EN) Rather than being separated along a single cleavage line between their adjacent ends, diode arrays (12) are spaced apart on a fabrication wafer (10) to allow parallel cleavage lines to be established between the ends of each adjacent pair of arrays by scribed grooves (18, 20; 40a, 40b; 48a, 48b) located along opposite sides of a narrow disposable strip (16) of wafer material. A cleaving technique substantially insures that any projecting lip (36) along the cleavage plane will be on the disposable strip rather than on a diode chip, so that such a defect cannot interfere with proper end-to-end spacing of the chips when they are subsequently assembled to provide a continuous row of chips with uniformly spaced individual light-emitting sites.
(FR) Plutôt que d'être séparés le long d'une seule ligne de clivage située entre leurs extrémités adjacentes, les réseaux de diodes (12) sont séparés les uns des autres sur une tranche (10) servant à leur fabrication, ce qui permet d'établir des lignes de séparation parallèles entre les extrémités de chaque paire adjacente de réseaux à l'aide de rainures tracées (18, 20; 40a, 40b; 48a, 48b) le long des côtés opposés d'une étroite bande inutilisée (16) de matériau de la tranche. La technique de séparation est telle qu'elle permet d'assurer que n'importe quel petit rebord (16) situé sur le plan de clivage se trouve sur la bande jetable plutôt que sur la puce de diode, de sorte qu'un tel défaut ne peut entraver l'espacement bout à bout correct des puces lorsqu'elles sont ensuite assemblées pour former une rangée continue de puces comprenant des sites individuels électroluminescents espacés de manière uniforme.
Designated States: JP
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0454837