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1. (WO1991007832) METHOD AND APPARATUS FOR CLOCK RECOVERY IN DIGITAL COMMUNICATION SYSTEMS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/007832 International Application No.: PCT/US1990/006638
Publication Date: 30.05.1991 International Filing Date: 13.11.1990
IPC:
H04L 7/027 (2006.01) ,H04L 7/033 (2006.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
027
extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
033
using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
Applicants:
DIGITAL EQUIPMENT CORPORATION [US/US]; 146 Main Street Maynard, MA 01754, US
Inventors:
PEARSON, Jonathan, D.; US
Agent:
NATH, Rama, B. ; Digital Equipment Corporation 111 Powdermill Road Maynard, MA 01754, US
Priority Data:
438,74916.11.1989US
Title (EN) METHOD AND APPARATUS FOR CLOCK RECOVERY IN DIGITAL COMMUNICATION SYSTEMS
(FR) PROCEDE ET APPAREIL DE RECUPERATION D'HORLOGE DANS DES SYSTEMES DE COMMUNICATIONS NUMERIQUES
Abstract:
(EN) A technique for recovering a clock from a digitally encoded communication signal uses a low-Q resonator and limiter for generating a coarse clock signal comprising a series of rectangular pulses at a frequency substantially equal to the clock (though subject to phase jitter), and a filter circuit, such as a phase-locked-loop ('PLL'), preferably employing a Sequential Phase/Frequency Detector to reduce the jitter superimposed on the coarse clock signal, so as to yield a well-behaved clock signal. By using a Sequential Phase/Frequency Detector, acquisition-aid circuitry generally is not required for the PLL.
(FR) Une technique de récupération d'une horloge à partir d'un signal de communication codée numériquement, utilise un résonateur de faible valeur Q ainsi qu'un limiteur afin de produire un signal d'horloge grossier comprenant une série d'impulsions rectangulaires à une fréquence sensiblement égale à celle de l'horloge (mais sujette à un sautillement de phase), et un circuit de filtrage, tel qu'une boucle à verrouillage de phase ('PLL'), employant de préférence un détecteur de phase/fréquence séquentielles, afin de réduire le sautillement superposé au signal d'horloge grossier, de manière à produire un signal d'horloge d'un bon comportement. Comme on utilise un détecteur de phase/fréquence séqentielles, le PLL ne nécessite pas de circuit d'aide d'acquisition.
Designated States: AU, CA, JP
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0453557CA2045166AU1991068961