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1. (WO1991007814) FULLY DIFFERENTIAL CMOS POWER AMPLIFIER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/007814 International Application No.: PCT/EP1990/001839
Publication Date: 30.05.1991 International Filing Date: 01.11.1990
Chapter 2 Demand Filed: 22.05.1991
IPC:
H03F 3/45 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
45
Differential amplifiers
Applicants:
ITALTEL SOCIETÀ ITALIANA TELECOMUNICAZIONI S.P.A. [IT/IT]; Piazzale Zavattari, 12 I-20149 Milano, IT (AllExceptUS)
MALOBERTI, Franco [IT/IT]; IT (UsOnly)
PALMISANO, Giuseppe [IT/IT]; IT (UsOnly)
SFORZINI, Luigi [IT/IT]; IT (UsOnly)
GAZZOLI, Giuseppe [IT/IT]; IT (UsOnly)
Inventors:
MALOBERTI, Franco; IT
PALMISANO, Giuseppe; IT
SFORZINI, Luigi; IT
GAZZOLI, Giuseppe; IT
Agent:
GIUSTINI, Delio; Italtel Società Italiana Telecomunicazioni S.p.A. P.O. Box 10 I-20019 Settimo Milanese, IT
Priority Data:
22362 A/8913.11.1989IT
Title (EN) FULLY DIFFERENTIAL CMOS POWER AMPLIFIER
(FR) AMPLIFICATEUR DE PUISSANCE CMOS ENTIEREMENT DIFFERENTIEL
Abstract:
(EN) Fully differential power amplifier comprising one high gain input stage (A1) and one AB class output stage (A2) realized in CMOS technology. Each of the two stages (A1, A2) is provided with a common mode feedback circuit (CMF1, CMF2) to set the working point thus optimizing the amplifier overall dynamic range. Besides a power dissipation reduction circuit (PWD) is provided to limit the power dissipated during the idle state of the power amplifier. In particular, the topology of the amplifier is fully symmetrical. In this way, a wide range output signal on a low resistive load, a very small harmonic distortion, as well as a low power consumption are achieved.
(FR) Amplificateur de puissance entièrement différentiel, comprenant un étage (A1) d'entrée de gain élevé et un étage (A2) de classe AB réalisés en technologie MOS complémentaire. Chacun des deux étages (A1, A2) est doté d'un circuit de réaction (CMF1, CMF2) de mode commun destiné à établir le point de travail, optimisant ainsi la gamme dynamique globale de l'amplificateur. De plus, on a prévu un circuit (BWD) de réduction de dissipation de puissance, destiné à limiter la puissance dissipée pendant l'état de repos de l'amplificateur de puissance. Notamment, la topologie de l'amplificateur est entièrement symétrique. Ainsi, on obtient un signal de sortie à gamme large sous une charge ohmique faible, une distorsion harmonique très faible, ainsi qu'une faible consommation de puissance.
Designated States: US
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0500694US5281924