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1. (WO1991007722) SYSTEM FOR MEMORY DATA INTEGRITY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1991/007722 International Application No.: PCT/US1990/006855
Publication Date: 30.05.1991 International Filing Date: 21.11.1990
IPC:
G06F 11/10 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
08
Error detection or correction by redundancy in data representation, e.g. by using checking codes
10
Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
Applicants:
UNISYS CORPORATION [US/US]; Township Line and Union Meeting Roads P.O. Box 500 Blue Bell, PA 19424, US
Inventors:
JEPPESEN, James, Henry, III; US
WHITTAKER, Bruce, Ernest; US
Agent:
STARR, Mark, T.; Unisys Corporation Township Line and Union Meeting Roads P.O. Box 500 Blue Bell, PA 19424, US
Priority Data:
440,82122.11.1989US
Title (EN) SYSTEM FOR MEMORY DATA INTEGRITY
(FR) SYSTEME DE CONSERVATION DE L'INTEGRITE DE DONNEES EN MEMOIRE
Abstract:
(EN) An expandable memory structure, both vertically and laterally, which uses a plurality of uniformly sized and duplicated chips which includes parity check functionality using an auxiliary parity memory chip of the same type and size. Selection circuitry permits choice of format for odd or even parity.
(FR) Une mémoire à structure extensible, aussi bien verticalement que latéralement, avec une pluralité de puces dédoublées de dimensions uniformes, assure la fonction de contrôle de parité au moyen d'une puce auxiliaire de stockage de la parité de même type et dimensions. Des circuits sélecteurs permettent de choisir des parités de format pair ou impair.
Designated States: JP
European Patent Office (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU, NL, SE)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0454836