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1. WO1991000571 - COMPUTER WITH CACHE

Publication Number WO/1991/000571
Publication Date 10.01.1991
International Application No. PCT/GB1990/001037
International Filing Date 05.07.1990
IPC
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
CPC
G06F 12/0844
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0844Multiple simultaneous or quasi-simultaneous cache accessing
Applicants
  • MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 2-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100, JP (AllExceptUS)
  • WRIGHT, David, Paul [GB/GB]; GB (UsOnly)
Inventors
  • WRIGHT, David, Paul; GB
Agents
  • FORRESTER KETLEY & CO.; Chamberlain House Paradise Place Birmingham B3 3HP, GB
Priority Data
8915422.305.07.1989GB
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) COMPUTER WITH CACHE
(FR) ORDINATEUR A ANTEMEMOIRE
Abstract
(EN)
A computer comprises a CPU (11), a memory store (12) and a cache comprising a cache memory (17) and a cache controller (16), the CPU (11) being capable of receiving from a memory store (12), or from the cache memory (17), elements of data each arranged as a plurality of words of data associated with a common address, the cache controller (16) inherently only being capable of handling elements of data arranged as a single word of data and an associated address, there being provided a state machine to enable the cache controller (16) to handle elements of data each arranged as a plurality of words of data associated with a common address.
(FR)
Ordinateur comprenant un processeur central (11), un bloc de mémoire (12), et une antémémoire composée d'une antémémoire (17) et d'une unité de contrôle de l'antémémoire (16). Le processeur central (11) est capable de recevoir, en provenance, soit du bloc de mémoire (12), soit de l'antémémoire (17) des éléments de données dont chacun est agencé en une pluralité de mots de données associés à une adresse commune. L'unité de contrôle de cadre (16) est la seule capable de traiter ces éléments arrangés en un seul mot de données associé à une adresse. Un automate fini permet à l'unité de contrôle de l'antémémoire (16) de traiter les éléments de données dont chacun est agencé en une pluralité de mots de données associés à une adresse commune.
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