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1. WO1991000568 - CONDITIONAL-SUM CARRY STRUCTURE COMPILER

Publication Number WO/1991/000568
Publication Date 10.01.1991
International Application No. PCT/US1990/003461
International Filing Date 22.06.1990
Chapter 2 Demand Filed 09.01.1991
IPC
G06F 7/50 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50Adding; Subtracting
G06F 17/50 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
50Computer-aided design
CPC
G06F 2207/4812
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
38Indexing scheme relating to groups G06F7/38 - G06F7/575
48Indexing scheme relating to groups G06F7/48 - G06F7/575
4802Special implementations
4812Multiplexers
G06F 30/30
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design [CAD]
30Circuit design
G06F 7/507
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50Adding; Subtracting
505in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
506with simultaneous carry generation for, or propagation over, two or more stages
507using selection between two conditionally calculated carry or sum values
Applicants
  • VLSI TECHNOLOGY, INC. [US/US]; 1109 McKay Drive San Jose, CA 95131, US
Inventors
  • ASATO, Creighton, Satoshi; US
  • DITZEN, Christoph; US
Agents
  • KREBS, Robert, E. ; Burns, Doane, Swecker & Mathis Post Office Box 1404 Alexandria, VA 22313-1404, US
Priority Data
370,55023.06.1989US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CONDITIONAL-SUM CARRY STRUCTURE COMPILER
(FR) COMPILATEUR POUR GENERER DES STRUCTURES DE REPORT DE SOMME CONDITIONNELLE
Abstract
(EN)
A conditional-sum carry structure (11) has architecture which is sufficiently regular that the structure can be conveniently generated by automated compiler. The carry structure (11) includes a column of input cells (left column), each of the cells (CC) in the column being operative for receiving binary numbers (A, B) and, for each of the received numbers, generating a sum bit (S) and two carry-out bits (C0, C1). Further the carry structure (11) includes an array of columns of binary logic elements comprised of dual multiplexers (MUX MUX elements), dual exclusive OR gates (XOR XOR elements), multiplixer and exclusive OR gate circuits (MUX XOR elements) and multiplixer units (ONE MUX elements) for receiving sum bits and carry-out bits from the input cells and for performing the operations of a conditional-sum carry structure (11).
(FR)
Une structure de report de somme conditionnelle (|1) présente une architecture suffisament régulière pour que ladite structure soit facilement générée par un compilateur automatique. Ladite structure de report (11) comprend une colonne de cellules d'entrée (colonne gauche), chaque cellule (CC) dans la colonne pouvant recevoir des nombres binaires (A, B). Lesdites cellules génèrent, pour chaque nombre reçu, un bit de somme (S) et deux bits de report à la sortie de colonnes d'éléments de logique binaires comportant des multiplexeurs doubles (éléments MUX MUX), des mélangeurs OU exclusifs doubles (éléments XOR XOR), des circuits de multiplexeurs et de mélangeurs OU exclusifs (éléments MUX XOR) et des unités multiplexeurs (éléments ONE MUX) pour recevoir des bits de somme et des bits de report à la sortie provenant des cellules d'entrée, et pour exécuter les opérations d'une structure de report de somme conditionnelle (11).
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