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1. (WO1990010983) TELECOMMUNICATIONS INTERFACE WITH IMPROVED JITTER REPORTING
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CLAIMS

What is claimed is:

1. A communications receiver, for receiving mcoming synchronous data streams, comprising:
a first clock recovery circuit, which generates a first estimated clock signal from the incoming data stream;
a second clock recovery circuit, which generates a second estimated clock signal from the mcoming data stream, said second estimated clock signal being more highly filtered than said first estimated clock signal and having substantiahy the same average frequency as said first estimated clock signal;
a first-in-first-out memory, configured to operate such that mcoming data is written, at times governed by said first clock signal, into an address location specified by a write-address-pointer value, and data is read out, at times governed by said second clock signal, from an address location specified by a read-address-pointer value;
and a jitter estimating circuit, comprising
a counter, clocked by one of said estimated clock signals, and
a memory device which latches the outputs of said counter whenever a predetermined one, of said read-address-pointer value and said write-address-pointer value, crosses a predetermined value,
wherein said counter is connected to be reset whenever the other, of said read-address-pointer value and said write-address-pointer value, crosses said predetermined value,
and wherein the output of said memory device is connected to provide an estimate of jitter.

2. The receiver of Claim 1, wherein said memory comprises an array of memory cells, and wherein addresses in said memory require at least five bits of data.

3. The receiver of Claim 1, wherein said memory is thirty-two bits deep.

4. The receiver of Claim 1, wherein said memory is at least ihirty-two bits deep, and wherein said counter is connected to be reset whenever the least significant bits of said write-address-point are equal to said predetermined value.

5. The receiver of Claim 1, wherein said counter is connected to be reset whenever said write-address-pointer value crosses zero.

6. The receiver of Claim 1, wherein said second clock recovery circuit is stabilized by a crystal resonator.

7. The receiver of Claim 1, wherein said memory carries exactly two bits of data in parallel.

8. The receiver of Claim 1, wherein said memory carries at least two bits of data in parallel at each said address thereof.

9. The receiver of Claim 1, wherein said estimate of jitter is fed back to control said second clock recovery circuit.

10. The receiver of Claim 1, wherein said predetermined value of said write-address-pointer at which said counter is reset is the same as said predeteπnined value of said read-address-pointer at which said counter output is latched.

11. The receiver of Claim 1, wherein said memory device is a latch.

12. The receiver of Claim 1, wherein said counter is an up-counter.

13. The receiver of Claim 1, wherein said counter is a down-counter.

14. The receiver of Claim 1, wherein said counter is clocked by said second estimated clock signal.

15. The receiver of Claim 1, wherein said memory device latches the outputs of said counter whenever said read-address-pointer value crosses said predetermined value.

16. The receiver of Claim 1, wherein said counter is connected to be reset whenever said write-address-pointer value crosses said predeteπnined value.

17. A communications receiver, for receiving mcoming synchronous data streams, comprising:
a first clock recovery circuit, which generates a first estimated clock signal from the mcoming data stream;
a second clock recovery circuit, which generates a second estimated clock signal from the mcoming data stream, said second estimated clock signal being more highly filtered than said first estimated clock signal and having substantiahy the same average frequency as said first estimated clock signal;
a serial-access memory, configured to operate such that
successive bits of the incoming data are written, with a timing governed by said first estimated clock signal, into address locations specified by the current value of a write-address-pointer which is incremented at each said write operation, and
successive bits are read out, with a timing governed by said second clock signal, from an address location specified by the current value of a read-address-pointer which is incremented at each said read operation;
and a counter,
clocked by said second estimated clock signal, and
connected to be reset whenever said write-address-pointer value crosses a predetermined value, and
having an output which is latched whenever said read-address-pointer value crosses a predetermined value, the successive latched outputs of said counter being connected to provide an estimate of jitter.

18. A communications receiver, for receiving mcoming synchronous data streams, comprising:
a clock recovery circuit, which generates a recovered clock signal from the mcoming data stream;
an elastic store memory, configured to write successive bits of the mcoming data, with a timing governed by said recovered clock signal, into address locations specified by the current value of a write-address-pointer which is incremented at each said write operation, and to read out successive bits, with a timing governed by a reference clock signal, from address locations specified by the current value of a read-address-pointer which is incremented at each said read operation; and
a counter, clocked by said second estimated clock signal, and connected to be reset whenever a predeteπnined one, of said read-address-pointer value and said write-address-pointer value, crosses a predetermined value, and having an output which is latched whenever the other one, of said read-address-pointer value and said write-address-pointer value, crosses a predeteπrhned value; the successive latched outputs of said counter being connected to provide an estimate of jitter.

19. A communications receiver, for receiving mcoming synchronous data streams, comprising:
a clock recovery circuit, which generates a recovered clock signal from the mcoming data stream;
an elastic store memory, configured to write successive bits of the mcoming data, with a timing governed by said recovered clock signal, into address locations specified by the current value of a write-address-pointer which is incremented at each said write operation, and to read out successive bits, with a timing governed by a reference clock signal, from address locations specified by the current value of a read-address-pointer which is incremented at each said read operation; and a jitter-estimating circuit, which outputs a jitter estimate corresponding to the instantaneous value of a first one of said address pointers, whenever the other of said address pointers equals a predetermined value.

20. A method for measuring jitter in an mcoming synchronous data stream, comprising the steps of:
buffering the mcoming data stream in an elastic store memory, using a write-address-pointer which indicates the current write location therein and a read-address-pointer which indicates the current read location therein;
reading data out of said elastic store memory with a timing governed by a reference clock;
providing a counter which is clocked by said reference clock; resetting said counter whenever said write-address-pointer value crosses a predetermined value; and
outputting the value of said counter whenever said read-address-pointer value crosses a predeteπnined value.

21. A method for receiving an incoming synchronous data stream, comprising the steps of:
connecting the incoming data stream to a clock recovery circuit, which generates a recovered clock signal therefrom;
writing successive bits of the mcoπnhg data into an elastic store memory, with a timing governed by said recovered clock signal, at address locations specified by the current value of a write-address-pointer; and incrementing said write-address-pointer at each said write operation;
and, concurrently with said writing operation, reading out successive bits from said elastic store memory, with a timing governed by a reference clock signal, from address locations which are specified by the current value of a read-address-pointer; and incrementing said read-address-pointer at each said read operation; and
estimating jitter in the incoming data stream, by latching and outputting the value of a counter whenever said read-address-pointer value crosses a predetermined value, and resetting said counter whenever said write-address-pointer value crosses a predetermined value.