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1. (WO1989000361) LEVEL CONVERSION CIRCUIT
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CLAIMS :

1. A level conversion circuit for converting ECL logic level signals to CMOS logic level signals, characterized by: a first MOS transistor (MPl), of first conductivity type, having source, drain, and gate electrodes, the source electrode being connected to receive ECL logic level signals; a second MOS transistor (MP2), of first conductivity type, having source, drain, and gate electrodes, the drain
electrode being connected to the gate electrode and the source electrode being connected to a biasing voltage, and the drain and gate electrodes being further connected to the gate electrode of said first MOS transistor (MPl); first and a second power
terminals (Vcc , VEE) having voltage levels thereat corresponding to high and low CMOS logic levels, respectively; a current sink connected between the drain and gate electrodes of said second MOS
transistor (MP2) and said second power terminal (VEE) ? a third MOS transistor (MNl), of second conductivity type, having source, drain, and gate electrodes, the drain electrode being connected to the drain electrode of said first MOS transistor (MPl), the source
electrode being connected to said second power
terminal (V E) an< the gate electrode being connected to said first power terminal (Vcc)/ an< a
complementary inverter circuit (MP3, MN3) connected between said first and said second power terminals ( cc, VEE) ' said inverter circuit having an input connected to the drain of said first MOS transistor (MPl) , and an output adapted to provide CMOS logic level signals in response to the ECL logic level signals at the source of said first MOS transistor (MPl).

2. A level conversion circuit according to claim 1, characterized in that said current sink includes a fourth MOS transistor (MN4), of second conductivity type, having source, drain, and gate electrodes, the drain being connected to the drain and gate of said second MOS transistor (MN2), and the source being connected to said second power terminal; fifth and sixth MOS transistors (MN5, MN6), of second conductivity type, having source, drain, and gate electrodes, the gate and drain electrodes of said fifth MOS transistor (.MN5) being connected to the gate electrode of said fourth MOS transistor (MN4), the drain and gate of said fifth MOS transistor (MN5), and the source of said sixth MOS transistor (MN6) being connected to said second power terminal (V E)» an<3 a seventh MOS transistor (MP4), of first conductivity type, having source, drain, and gate electrodes, the gate electrode being connected to said second power terminal (V E)/ the source electrode being connected to said first power terminal (Vcc) ani-- the drain being connected to the gate of said fourth MOS transistor (MN4)

3. A level conversion circuit according to claim 1, characterized in that said current sink includes a resistor (RgiNK) connected between the drain electrode of said second MOS transistor (MP2) and said second power terminal (VEE) •

4. A level conversion circuit according to claim 1, characterized in that said complementary inverter circuit includes: a P-channel MOS transistor (MP3), having source, drain, and gate electrodes; and an N-channel MOS transistor (MN3), having source, drain, and gate electrodes, the gate electrode being connected to the gate electrode of said P-channel MOS transistor (MP3) and the drain of said first MOS transistor (MPl), the drain and source of said P-channel and said N-channel MOS transistors (MP3, MN3), respectively, being connected together to provide an output, the source and drain of said P-channel and said N-channel MOS transistors (MP3, MN3),
respectively, being connected to said first and said second power terminals (Veer VEE)-- respectively.

5. A level conversion circuit according to claim 1, characterized in that the size of said first MOS transistor (MPl) is equal to the size of said second MOS transistor (MP2).

6. A level conversion circuit according to claim 1, characterized in that the biasing voltage is fixed at one-half the sum of the voltage levels of the ECL low logic level signal and the ECL high logic level signal.