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Machine translation
1. (WO1988007297) ASYNCHRONOUS TIME DIVISION COMMUNICATION SYSTEM
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1988/007297    International Application No.:    PCT/EP1988/000178
Publication Date: 22.09.1988 International Filing Date: 05.03.1988
Chapter 2 Demand Filed:    31.10.1988    
IPC:
G06F 5/06 (2006.01), H04J 3/06 (2006.01), H04L 12/54 (2013.01), H04L 7/10 (2006.01)
Applicants: ALCATEL N.V. [NL/NL]; World Trade Center, Strawinskylaan 537, NL-1077 XX Amsterdam (NL) (AT, AU, BE, CH, DE, FI, FR, GB, IT, JP, KR, LU, NL, SE only).
BELL TELEPHONE MANUFACTURING COMPANY, NAAMLOZE VEN [BE/BE]; NOOTSCHAP;, Francis Wellesplein 1;, B-2018 Antwerp (BE) (BE only).
DE PRYCKER, Martin, Louis, Florence [BE/BE]; (BE) (For US Only).
RYCKEBUSCH, Mark, Lucien, Marie, Roger [BE/BE]; (BE) (For US Only).
BARRI, Peter, Irma, August [BE/BE]; (BE) (For US Only)
Inventors: DE PRYCKER, Martin, Louis, Florence; (BE).
RYCKEBUSCH, Mark, Lucien, Marie, Roger; (BE).
BARRI, Peter, Irma, August; (BE)
Agent: ROSENOER, Jacques @;; Patent Department;, Bell Telephone Manufacturing Company, Naamloze Ven, nootschap;, Francis Wellesplein 1;, B-2018 Antwerp (BE)
Priority Data:
8700282 18.03.1987 BE
Title (EN) ASYNCHRONOUS TIME DIVISION COMMUNICATION SYSTEM
(FR) SYSTEME DE COMMUNICATION A PARTAGE DE TEMPS ASYNCHRONE
Abstract: front page image
(EN)Asynchronous time division communication system wherein user stations (US1/2), each with an associated send and receive circuit (SEND1/2, REC1/2), are coupled with a packet switching network (PSN). Each send circuit includes a send clock (OSC) and each receive circuit is provided with a receive clock (POSC), controlling the reading of a packet buffer circuit (PFIFO), and with a computer (COMP) which regulates the receive clock (POSC) in such a way that the filling level of the buffer circuit remains substantially constant.
(FR)Système de communication à partage de temps asynchrone dans lequel des stations utilisatrices (US1/2), dont chacune possède un circuit de transmission et un circuit de réception associés (SEND1/2, REC1/2), sont reliées à un réseau de commutation de paquets (PSN). Chaque circuit de transmission comporte une horloge de transmission (OSC) et chaque circuit de réception est muni d'une horloge de réception (POSC), qui commande la lecture d'un circuit tampon des paquets (PFIFO), et d'un ordinateur (COMP) qui règle l'horloge de réception (POSC) de manière que le niveau de remplissage du circuit tampon reste sensiblement constant.
Designated States: AU, FI, JP, KR, US.
European Patent Office (AT, BE, CH, DE, FR, GB, IT, LU, NL, SE).
Publication Language: English (EN)
Filing Language: English (EN)