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Machine translation
1. (WO1987006370) INTERRUPT CONTROL METHOD IN A MULTIPROCESSOR SYSTEM
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1987/006370    International Application No.:    PCT/JP1987/000225
Publication Date: 22.10.1987 International Filing Date: 10.04.1987
IPC:
G06F 13/24 (2006.01), G06F 15/17 (2006.01)
Applicants: FANUC LTD [JP/JP]; 3580, Shibokusa Aza Komanba, Oshinomura, Minamitsuru-gun, Yamanashi 401-05 (JP) (For All Designated States Except US).
YONEKURA, Mikio [JP/JP]; (JP) (For US Only).
KINOSHITA, Jiro [JP/JP]; (JP) (For US Only)
Inventors: YONEKURA, Mikio; (JP).
KINOSHITA, Jiro; (JP)
Agent: HATTORI, Kiyoshi; Hattori Patent Office, 3F. Kato Bldg., 11-4, Yokoyama-cho, Hachioji-shi, Tokyo 192 (JP)
Priority Data:
61/86921 15.04.1986 JP
Title (EN) INTERRUPT CONTROL METHOD IN A MULTIPROCESSOR SYSTEM
(FR) PROCEDE DE COMMANDE D'INTERRUPTION DANS UN SYSTEME MULTIPROCESSEUR
Abstract: front page image
(EN)An interrupt control method in a multiprocessor system wherein a plurality of processors (21, 31, 41) and an interface circuit (10) that generates interrupt are connected to a bus of a single system. Using particular address spaces (Addr1, Addr2, Addr3) as interrupt addresses, the processors select mask bits that correspond to said address spaces, store said mask bits in the registers (24, 34, 44) of said processors, and a bus cycle generating circuit in the interface circuit (10) occupies a bus upon receipt of an interrupt signal, indicates its own cause of interrupt, and writes a bit corresponding to said address space onto an address bus. The processors (21, 22, 23) recognize the interrupt from bits of said addresses corresponding to the address spaces (Addr1, Addr2, Addr3) and from the mask bits of said registers (24, 34, 44).
(FR)Dans le procédé ci-décrit, une pluralité de processeurs (21, 31, 41) et un circuit d'interface (10) générant des interruptions sont connectés à un bus d'un seul système. A l'aide d'espaces d'adresse particuliers (Addr1, Addr2, Addr3) servant d'adresses d'interruption, les processeurs sélectionnent des bits de masque qui correspondent auxdits espaces d'adresse, stockent lesdits bits de masque dans les registres (24, 34, 44) desdits processeurs, et un circuit générateur de cycle de bus dans le circuit d'interface (10) occupe un bus dès réception d'un signal d'interruption, indique sa propre cause d'interruption, et écrit un bit correspondant auxdits espaces d'adresse sur un un bus d'adresse. Les processeurs (21, 22, 23) reconnaissent les interruptions à partir des bits desdites adresses correspondants aux espaces d'adresse (Addr1, Addr2, Addr3) et à partir des bits de masque desdits registres (23, 34, 44).
Designated States: US.
European Patent Office (DE, FR, GB).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)