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1. (WO1987003758) TEMPERATURE COMPENSATED CMOS TO ECL LOGIC LEVEL TRANSLATOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/1987/003758 International Application No.: PCT/US1986/002532
Publication Date: 18.06.1987 International Filing Date: 24.11.1986
IPC:
H03K 19/003 (2006.01) ,H03K 19/0185 (2006.01) ,H01L 27/02 (2006.01)
[IPC code unknown for H03K 19/03]
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
0185
using field-effect transistors only
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
Applicants:
NCR CORPORATION [US/US]; World Headquarters Dayton, OH 45479, US
Inventors:
LAUFFER, Donald, Keith; US
SANWO, Ikuo, Jimmy; US
Agent:
DUGAS, Edward @; Intellectual Property Section Law Department, NCR Corporation World Headquarters Dayton, OH 45479, US
Priority Data:
809,10816.12.1985US
Title (EN) TEMPERATURE COMPENSATED CMOS TO ECL LOGIC LEVEL TRANSLATOR
(FR) TRADUCTEUR THERMOCOMPENSE DE SIGNAUX DE NIVEAUX LOGIQUES CMOS A ECL
Abstract:
(EN) A CMOS to ECL interface circuit includes a pair of series connected complementary transistors (14, 16) having input CMOS logic levels applied to their gates and output ECL logic levels derived from the junction point of their source-drain paths. The transistors (14, 16) are connected between power supply terminals (VA, VB) which are coupled to the outputs of an OR-NOR gate (20) included in the same temperature environment as the ECL logic circuits serviced by the interface circuit. Thus, temperature compensation is achieved since the power supply applied to the power supply terminals (VA, VB) of the interface circuit automatically tracks variations in the ECL output logic level resulting from temperature variations.
(FR) Un circuit d'interface CMOS à ECL comprend une paire de transistors complémentaires reliés en série (14, 16) aux portes desquels on applique des signaux de niveaux logiques CMOS d'entrée, tout en dérivant du point de jonction de leur chemin source/drain des signaux de niveaux logiques ECL de sortie. Les transistors (14, 16) sont connectés entre des bornes d'alimentation (VA, VB) qui sont couplées aux sorties d'une porte OU-NI (20) située dans le mêmem environnement thermique que les circuits logiques ECL desservis par le circuit d'interface. La compensation thermique est ainsi réalisée du fait que l'alimentation appliquée aux bornes (VA, VB) du circuit d'interface suit automatiquement les variations du niveau logique de sortie ECL résultant des variations de température.
Designated States: JP
European Patent Office (DE, FR, GB)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP0252931