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Machine translation
1. (WO1987001218) INTEGRATED-CIRCUIT HAVING TWO NMOS DEPLETION MODE TRANSISTORS FOR PRODUCING A STABLE DC VOLTAGE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1987/001218    International Application No.:    PCT/US1986/001603
Publication Date: 26.02.1987 International Filing Date: 06.08.1986
IPC:
G05F 3/24 (2006.01)
Applicants: EASTMAN KODAK COMPANY [US/US]; 343 State Street, Rochester, NY 14650 (US)
Inventors: STEVENS, Eric, G.; (US)
Agent: OWENS, Raymond, L.; 343 State Street, Rochester, NY 14650 (US)
Priority Data:
766,994 19.08.1985 US
Title (EN) INTEGRATED-CIRCUIT HAVING TWO NMOS DEPLETION MODE TRANSISTORS FOR PRODUCING A STABLE DC VOLTAGE
(FR) CIRCUIT INTEGRE COMPORTANT DEUX TRANSISTORS NMOS A DEPLETION POUR PRODUIRE UNE TENSION CONTINUE STABLE
Abstract: front page image
(EN)An integrated-circuit including two NMOS depletion mode transistors Q¿1?, Q¿2? having parameters selected so that when the transistors are connected in accordance with the invention, the circuit (10) in response to a variable input DC voltage produces a stable DC output voltage.
(FR)Circuit intégré comportant deux transistors à déplétion NMOS Q¿1?, Q¿2?, leurs paramètres étant choisis de manière que, lorsque les transistors sont connectés de la manière prévue par l'invention, le circuit (10) produise une tension de sortie continue stable en réponse à une tension continue d'entrée variable.
Designated States: JP.
European Patent Office (DE, FR, GB).
Publication Language: English (EN)
Filing Language: English (EN)