Search International and National Patent Collections

1. (WO1985005471) DATA TRANSFER EQUIPMENT

Pub. No.:    WO/1985/005471    International Application No.:    PCT/JP1985/000267
Publication Date: Dec 5, 1985 International Filing Date: May 15, 1985
IPC: G05B 19/414
G06F 13/42
Applicants: FANUC LTD

IKEDA, Yoshiaki

KUWASAWA, Mitsuru

Inventors: IKEDA, Yoshiaki

KUWASAWA, Mitsuru

Title: DATA TRANSFER EQUIPMENT
Abstract:
The invention transfers serial data sent from a first apparatus (10) onto predetermined bits of predetermined addresses of RAM (300) of a second apparatus (30) for each of the bits. Data transfer equipment transfers each of the bits data in serial data from the first apparatus (10) onto predetermined bits of predetermined addresses of RAM (300) in the second apparatus (30) in synchronism with clock pulses sent from the first apparatus (10), and comprises: a counter (206) that is incremented by said clock pulses; an address generating circuit (210) which generates address of said RAM (300) responding to the output of said counter (206); a bit address generating circuit (211) which generates a bit address to designate a bit position in an address of said RAM (300) responsive to the output of said counter (206); a timing control circuit (209) which generates a timing signal for a read cycle and for a subsequent write cycle responsive to the output of said counter (206) during a period in which an address is being generated by said address generating circuit (210); and a read modify write circuit (214) which replaces data of a bit position designated by a bit address of said bit address generating circuit (211) by a corresponding bit data of serial data sent from the first apparatus (10) among a plurality of bits in parallel data corresponding to the address (210) of said address generating circuit read from said RAM (300) during the read cycle specified by said timing control circuit (209), and which transfers said parallel data that is replaced onto the original address of said RAM during the write cycle specified by said timing control circuit (209), such that individual bits of serial data sent from the first apparatus (10) are transferred to predetermined bits of predetermined addresses of RAM (300) in the second apparatus (30).